[PULL,15/38] target/riscv: Set VS bits in mideleg for Hyp extension

Commit Message

Palmer Dabbelt March 3, 2020, 12:48 a.m. UTC

From: Alistair Francis <[e-mail]>

Signed-off-by: Alistair Francis <[e-mail]>
Reviewed-by: Palmer Dabbelt <[e-mail]>
Signed-off-by: Palmer Dabbelt <[e-mail]>
---
 target/riscv/csr.c | 3 +++
 1 file changed, 3 insertions(+)

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f7333286bd..c0e942684d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -448,6 +448,9 @@  static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
 {
     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
+    if (riscv_has_ext(env, RVH)) {
+        env->mideleg |= VS_MODE_INTERRUPTS;
+    }
     return 0;
 }