From patchwork Fri Mar 13 03:23:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chen Qun X-Patchwork-Id: 11435917 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7E55B92A for ; Fri, 13 Mar 2020 03:24:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5EE0F20724 for ; Fri, 13 Mar 2020 03:24:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5EE0F20724 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCavx-0005Ty-9y for patchwork-qemu-devel@patchwork.kernel.org; Thu, 12 Mar 2020 23:24:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35933) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCavU-0004dt-2n for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:23:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCavS-0000mf-Qx for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:23:55 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:3282 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCavS-0000cs-Fa; Thu, 12 Mar 2020 23:23:54 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id A2495D93C612C1A163E7; Fri, 13 Mar 2020 11:23:47 +0800 (CST) Received: from huawei.com (10.133.205.93) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:23:39 +0800 From: Chen Qun To: , Subject: [PATCH v3] hw/net/imx_fec: write TGSR and TCSR3 in imx_enet_write() Date: Fri, 13 Mar 2020 11:23:27 +0800 Message-ID: <20200313032327.7008-1-kuhn.chenqun@huawei.com> X-Mailer: git-send-email 2.21.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.133.205.93] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , zhang.zhanghailiang@huawei.com, Jason Wang , Peter Chubb , Euler Robot , Chen Qun Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The current code causes clang static code analyzer generate warning: hw/net/imx_fec.c:858:9: warning: Value stored to 'value' is never read value = value & 0x0000000f; ^ ~~~~~~~~~~~~~~~~~~ hw/net/imx_fec.c:864:9: warning: Value stored to 'value' is never read value = value & 0x000000fd; ^ ~~~~~~~~~~~~~~~~~~ According to the definition of the function, the two “value” assignments should be written to registers. Reported-by: Euler Robot Signed-off-by: Chen Qun --- Cc: Peter Maydell Cc: Jason Wang Cc: Peter Chubb v1->v2: The register 'ENET_TGSR' write-1-to-clear timer flag. The register 'ENET_TCSRn' 7bit(TF) write-1-to-clear timer flag. v2->v3: Optimize code style, based on discussions with Peter. --- hw/net/imx_fec.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 6a124a154a..3547975710 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -854,14 +854,17 @@ static void imx_enet_write(IMXFECState *s, uint32_t index, uint32_t value) s->regs[index] = value & 0x00007f7f; break; case ENET_TGSR: - /* implement clear timer flag */ - value = value & 0x0000000f; + /* implement clear timer flag, 0-3 bits W1C, reserved bits write zero */ + s->regs[index] &= ~(value & 0x0000000f) & 0x0000000f; break; case ENET_TCSR0: case ENET_TCSR1: case ENET_TCSR2: case ENET_TCSR3: - value = value & 0x000000fd; + /* 7 bits W1C, reserved bits write zero */ + s->regs[index] &= ~(value & 0x00000080) & 0x000000ff; + s->regs[index] &= ~0x0000007d; /* writable fields */ + s->regs[index] |= (value & 0x0000007d); break; case ENET_TCCR0: case ENET_TCCR1: