diff mbox series

[v2,1/1] target/arm: Drop access_el3_aa32ns()

Message ID 20200504142125.31180-2-edgar.iglesias@gmail.com (mailing list archive)
State New, archived
Headers show
Series target/arm: Remove access_el3_aa32ns() | expand

Commit Message

Edgar E. Iglesias May 4, 2020, 2:21 p.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Calling access_el3_aa32ns() works for AArch32 only cores
but it does not handle 32-bit EL2 on top of 64-bit EL3
for mixed 32/64-bit cores.

Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
and only use the latter.

Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/arm/helper.c | 30 +++++++-----------------------
 1 file changed, 7 insertions(+), 23 deletions(-)

Comments

Edgar E. Iglesias May 4, 2020, 5:07 p.m. UTC | #1 
On Mon, May 04, 2020 at 04:21:25PM +0200, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Calling access_el3_aa32ns() works for AArch32 only cores
> but it does not handle 32-bit EL2 on top of 64-bit EL3
> for mixed 32/64-bit cores.
> 
> Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
> and only use the latter.


Forgot to update the Subject/Summary to reflect that
access_el3_aa32ns_aa64any() is now being removed.

Will fix in v3...




> 
> Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2")
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
>  target/arm/helper.c | 30 +++++++-----------------------
>  1 file changed, 7 insertions(+), 23 deletions(-)
> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index dfefb9b3d9..7d21bf1cc7 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -502,35 +502,19 @@ void init_cpreg_list(ARMCPU *cpu)
>  }
>  
>  /*
> - * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
> - * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
> - *
> - * access_el3_aa32ns: Used to check AArch32 register views.
> - * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
> + * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
>   */
>  static CPAccessResult access_el3_aa32ns(CPUARMState *env,
>                                          const ARMCPRegInfo *ri,
>                                          bool isread)
>  {
> -    bool secure = arm_is_secure_below_el3(env);
> -
> -    assert(!arm_el_is_aa64(env, 3));
> -    if (secure) {
> +    if (!is_a64(env) && arm_current_el(env) == 3 &&
> +        arm_is_secure_below_el3(env)) {
>          return CP_ACCESS_TRAP_UNCATEGORIZED;
>      }
>      return CP_ACCESS_OK;
>  }
>  
> -static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
> -                                                const ARMCPRegInfo *ri,
> -                                                bool isread)
> -{
> -    if (!arm_el_is_aa64(env, 3)) {
> -        return access_el3_aa32ns(env, ri, isread);
> -    }
> -    return CP_ACCESS_OK;
> -}
> -
>  /* Some secure-only AArch32 registers trap to EL3 if used from
>   * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
>   * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
> @@ -5236,7 +5220,7 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
>      { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
> -      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +      .access = PL2_RW, .accessfn = access_el3_aa32ns,
>        .type = ARM_CP_CONST, .resetvalue = 0 },
>      { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
>        .cp = 15, .opc1 = 6, .crm = 2,
> @@ -5284,7 +5268,7 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>        .type = ARM_CP_CONST, .resetvalue = 0 },
>      { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
> -      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +      .access = PL2_RW, .accessfn = access_el3_aa32ns,
>        .type = ARM_CP_CONST, .resetvalue = 0 },
>      { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
> @@ -7626,12 +7610,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>              ARMCPRegInfo vpidr_regs[] = {
>                  { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
>                    .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
> -                  .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
>                    .type = ARM_CP_CONST, .resetvalue = cpu->midr,
>                    .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
>                  { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
>                    .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
> -                  .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
> +                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
>                    .type = ARM_CP_NO_RAW,
>                    .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
>                  REGINFO_SENTINEL
> -- 
> 2.20.1
>
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index dfefb9b3d9..7d21bf1cc7 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -502,35 +502,19 @@  void init_cpreg_list(ARMCPU *cpu)
 }
 
 /*
- * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
- * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
- *
- * access_el3_aa32ns: Used to check AArch32 register views.
- * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
+ * Some registers are not accessible from AArch32 EL3 if SCR.NS == 0.
  */
 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
                                         const ARMCPRegInfo *ri,
                                         bool isread)
 {
-    bool secure = arm_is_secure_below_el3(env);
-
-    assert(!arm_el_is_aa64(env, 3));
-    if (secure) {
+    if (!is_a64(env) && arm_current_el(env) == 3 &&
+        arm_is_secure_below_el3(env)) {
         return CP_ACCESS_TRAP_UNCATEGORIZED;
     }
     return CP_ACCESS_OK;
 }
 
-static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
-                                                const ARMCPRegInfo *ri,
-                                                bool isread)
-{
-    if (!arm_el_is_aa64(env, 3)) {
-        return access_el3_aa32ns(env, ri, isread);
-    }
-    return CP_ACCESS_OK;
-}
-
 /* Some secure-only AArch32 registers trap to EL3 if used from
  * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
  * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
@@ -5236,7 +5220,7 @@  static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+      .access = PL2_RW, .accessfn = access_el3_aa32ns,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
       .cp = 15, .opc1 = 6, .crm = 2,
@@ -5284,7 +5268,7 @@  static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
-      .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+      .access = PL2_RW, .accessfn = access_el3_aa32ns,
       .type = ARM_CP_CONST, .resetvalue = 0 },
     { .name = "HSTR_EL2", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 3,
@@ -7626,12 +7610,12 @@  void register_cp_regs_for_features(ARMCPU *cpu)
             ARMCPRegInfo vpidr_regs[] = {
                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
-                  .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+                  .access = PL2_RW, .accessfn = access_el3_aa32ns,
                   .type = ARM_CP_NO_RAW,
                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
                 REGINFO_SENTINEL