| Message ID | 20200510014250.28111-3-weijiang.yang@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable CET support for guest | expand |
On 5/10/2020 9:42 AM, Yang Weijiang wrote: > CET SHSTK/IBT MSRs can be saved/restored with XSAVES/XRSTORS, but > currently the related feature words are not supported, so add the > new entries. XSAVES/RSTORS always use compacted storage format, which > means the supervisor states' offsets are always 0, ignore them while > calculating stardard format storage size. > > Signed-off-by: Zhang Yi <yi.z.zhang@linux.intel.com> > Signed-off-by: Yang Weijiang <weijiang.yang@intel.com> > --- > target/i386/cpu.c | 38 ++++++++++++++++++++++++++++++++++++-- > 1 file changed, 36 insertions(+), 2 deletions(-) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 90ffc5f3b1..3174e05482 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -965,7 +965,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > .type = CPUID_FEATURE_WORD, > .feat_names = { > NULL, "avx512vbmi", "umip", "pku", > - NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, > + NULL /* ospke */, "waitpkg", "avx512vbmi2", "shstk", > "gfni", "vaes", "vpclmulqdq", "avx512vnni", > "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, > "la57", NULL, NULL, NULL, > @@ -988,7 +988,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > NULL, NULL, "md-clear", NULL, > NULL, NULL, NULL, NULL, > NULL, NULL, NULL /* pconfig */, NULL, > - NULL, NULL, NULL, NULL, > + "ibt", NULL, NULL, NULL, > NULL, NULL, "spec-ctrl", "stibp", > NULL, "arch-capabilities", "core-capability", "ssbd", > }, > @@ -1069,6 +1069,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > }, > .tcg_features = TCG_XSAVE_FEATURES, > }, > + /* Below are xsaves feature words */ > + [FEAT_XSAVES_LO] = { > + .type = CPUID_FEATURE_WORD, > + .cpuid = { > + .eax = 0xD, > + .needs_ecx = true, > + .ecx = 1, > + .reg = R_ECX, > + }, > + .migratable_flags = XSTATE_CET_U_MASK, why exclude XSTATE_CET_S_MASK? Is any reason why it not migratable? > + }, > + [FEAT_XSAVES_HI] = { > + .type = CPUID_FEATURE_WORD, > + .cpuid = { > + .eax = 0xD, > + .needs_ecx = true, > + .ecx = 1, > + .reg = R_EDX > + }, > + }, > [FEAT_6_EAX] = { > .type = CPUID_FEATURE_WORD, > .feat_names = { > @@ -1455,6 +1475,14 @@ static const ExtSaveArea x86_ext_save_areas[] = { > { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, > .offset = offsetof(X86XSaveArea, pkru_state), > .size = sizeof(XSavePKRU) }, > + [XSTATE_CET_U_BIT] = { > + .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_CET_SHSTK, > + .offset = 0 /*supervisor mode component, offset = 0 */, > + .size = sizeof(XSavesCETU) }, > + [XSTATE_CET_S_BIT] = { > + .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_CET_SHSTK, > + .offset = 0 /*supervisor mode component, offset = 0 */, > + .size = sizeof(XSavesCETS) }, > }; > > static uint32_t xsave_area_size(uint64_t mask) > @@ -1465,6 +1493,9 @@ static uint32_t xsave_area_size(uint64_t mask) > for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { > const ExtSaveArea *esa = &x86_ext_save_areas[i]; > if ((mask >> i) & 1) { > + if (i >= 2 && !esa->offset) { > + continue; > + } > ret = MAX(ret, esa->offset + esa->size); > } > } > @@ -6008,6 +6039,9 @@ static void x86_cpu_reset(DeviceState *dev) > } > for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { > const ExtSaveArea *esa = &x86_ext_save_areas[i]; > + if (!esa->offset) { > + continue; > + } > if (env->features[esa->feature] & esa->bits) { > xcr0 |= 1ull << i; > } >
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 90ffc5f3b1..3174e05482 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -965,7 +965,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .type = CPUID_FEATURE_WORD, .feat_names = { NULL, "avx512vbmi", "umip", "pku", - NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, + NULL /* ospke */, "waitpkg", "avx512vbmi2", "shstk", "gfni", "vaes", "vpclmulqdq", "avx512vnni", "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, @@ -988,7 +988,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, "md-clear", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL /* pconfig */, NULL, - NULL, NULL, NULL, NULL, + "ibt", NULL, NULL, NULL, NULL, NULL, "spec-ctrl", "stibp", NULL, "arch-capabilities", "core-capability", "ssbd", }, @@ -1069,6 +1069,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { }, .tcg_features = TCG_XSAVE_FEATURES, }, + /* Below are xsaves feature words */ + [FEAT_XSAVES_LO] = { + .type = CPUID_FEATURE_WORD, + .cpuid = { + .eax = 0xD, + .needs_ecx = true, + .ecx = 1, + .reg = R_ECX, + }, + .migratable_flags = XSTATE_CET_U_MASK, + }, + [FEAT_XSAVES_HI] = { + .type = CPUID_FEATURE_WORD, + .cpuid = { + .eax = 0xD, + .needs_ecx = true, + .ecx = 1, + .reg = R_EDX + }, + }, [FEAT_6_EAX] = { .type = CPUID_FEATURE_WORD, .feat_names = { @@ -1455,6 +1475,14 @@ static const ExtSaveArea x86_ext_save_areas[] = { { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, .offset = offsetof(X86XSaveArea, pkru_state), .size = sizeof(XSavePKRU) }, + [XSTATE_CET_U_BIT] = { + .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_CET_SHSTK, + .offset = 0 /*supervisor mode component, offset = 0 */, + .size = sizeof(XSavesCETU) }, + [XSTATE_CET_S_BIT] = { + .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_CET_SHSTK, + .offset = 0 /*supervisor mode component, offset = 0 */, + .size = sizeof(XSavesCETS) }, }; static uint32_t xsave_area_size(uint64_t mask) @@ -1465,6 +1493,9 @@ static uint32_t xsave_area_size(uint64_t mask) for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa = &x86_ext_save_areas[i]; if ((mask >> i) & 1) { + if (i >= 2 && !esa->offset) { + continue; + } ret = MAX(ret, esa->offset + esa->size); } } @@ -6008,6 +6039,9 @@ static void x86_cpu_reset(DeviceState *dev) } for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa = &x86_ext_save_areas[i]; + if (!esa->offset) { + continue; + } if (env->features[esa->feature] & esa->bits) { xcr0 |= 1ull << i; }