[2/2] target/xtensa: fix simcall for newer hardware

Commit Message

Max Filippov May 17, 2020, 9:58 p.m. UTC

After Xtensa release RE.2 simcall opcode has become nop for the
hardware instead of illegal instruction.

Signed-off-by: Max Filippov <[e-mail]>
---
 target/xtensa/translate.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

Patch

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 546d2fa2facf..4bc15252c8a5 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2367,9 +2367,10 @@  static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[],
 #ifdef CONFIG_USER_ONLY
     bool ill = true;
 #else
-    bool ill = !semihosting_enabled();
+    /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
+    bool ill = dc->config->hw_version <= 250002 && !semihosting_enabled();
 #endif
-    if (ill) {
+    if (ill || !semihosting_enabled()) {
         qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
     }
     return ill;
@@ -2379,7 +2380,9 @@  static void translate_simcall(DisasContext *dc, const OpcodeArg arg[],
                               const uint32_t par[])
 {
 #ifndef CONFIG_USER_ONLY
-    gen_helper_simcall(cpu_env);
+    if (semihosting_enabled()) {
+        gen_helper_simcall(cpu_env);
+    }
 #endif
 }