diff mbox series

[v5,4/4] target/i386: modify Icelake-Server CPU model number

Message ID 20200619073114.24303-5-chenyi.qiang@intel.com (mailing list archive)
State New, archived
Headers show
Series modify CPU model info | expand

Commit Message

Chenyi Qiang June 19, 2020, 7:31 a.m. UTC
According to the Intel Icelake family list, Icelake-Server uses model
number 106(0x6A).

Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>
---
 target/i386/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Eduardo Habkost July 9, 2020, 10:12 p.m. UTC | #1
On Fri, Jun 19, 2020 at 03:31:14PM +0800, Chenyi Qiang wrote:
> According to the Intel Icelake family list, Icelake-Server uses model
> number 106(0x6A).
> 
> Signed-off-by: Chenyi Qiang <chenyi.qiang@intel.com>

Same question as in patch 1/4: why are you changing v1 instead of
adding a new version?


> ---
>  target/i386/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 3c81ca543f..f919607fa0 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3384,7 +3384,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>          .level = 0xd,
>          .vendor = CPUID_VENDOR_INTEL,
>          .family = 6,
> -        .model = 134,
> +        .model = 106,
>          .stepping = 0,
>          .features[FEAT_1_EDX] =
>              CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> -- 
> 2.17.1
> 
>
diff mbox series

Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3c81ca543f..f919607fa0 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3384,7 +3384,7 @@  static X86CPUDefinition builtin_x86_defs[] = {
         .level = 0xd,
         .vendor = CPUID_VENDOR_INTEL,
         .family = 6,
-        .model = 134,
+        .model = 106,
         .stepping = 0,
         .features[FEAT_1_EDX] =
             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |