From patchwork Fri Jun 26 23:55:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Havard Skinnemoen X-Patchwork-Id: 11629113 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1BD796C1 for ; Fri, 26 Jun 2020 23:58:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E71DC2075A for ; Fri, 26 Jun 2020 23:58:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="GLMttdIZ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E71DC2075A Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:49622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1joyEz-00054E-54 for patchwork-qemu-devel@patchwork.kernel.org; Fri, 26 Jun 2020 19:58:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3B4v2XgsKCvQdogejjaikajckkcha.Ykimaiq-Zarahjkjcjq.knc@flex--hskinnemoen.bounces.google.com>) id 1joyCJ-0007o3-Lu for qemu-devel@nongnu.org; Fri, 26 Jun 2020 19:55:55 -0400 Received: from mail-pg1-x549.google.com ([2607:f8b0:4864:20::549]:54515) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3B4v2XgsKCvQdogejjaikajckkcha.Ykimaiq-Zarahjkjcjq.knc@flex--hskinnemoen.bounces.google.com>) id 1joyCH-00027o-Jm for qemu-devel@nongnu.org; Fri, 26 Jun 2020 19:55:55 -0400 Received: by mail-pg1-x549.google.com with SMTP id z16so7716543pgh.21 for ; Fri, 26 Jun 2020 16:55:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=date:in-reply-to:message-id:mime-version:references:subject:from:to :cc:content-transfer-encoding; bh=VY3rbt0GvJaQReeiX7aDk07oAXrwlgq2RUExTgOvm3A=; b=GLMttdIZy+26BuSfCND6TPUln39J3DVt3X4W7Sgrd5dpJuKk/3RzIsv2XbIcwIJ7Cf Wgfp5xQH7AgYQkDq4DVrfi6LeEyu0wqMsjAYmtqpKG7e3YiddRABGeYEZp0CzOlstcac Hy/lqbfCNtoEut0wyDB1UuYxAz6ZBDKCP1uovX34FHLJJAz1Tu04vYB4/0d30HQ1vh35 6jNiM02UBuOOSKDj9nBIeHOtlOm4YeQmA88asKCZBHRnv4CsSBiH3CjJYwf7AoJoxGv7 Zuo9TW7wFPGiI0Aoap8dBGRld11ecA3YUJTsIP0KN/bFxvxumV7sN57/oy0IHC9zEVwK OTNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:in-reply-to:message-id:mime-version :references:subject:from:to:cc:content-transfer-encoding; bh=VY3rbt0GvJaQReeiX7aDk07oAXrwlgq2RUExTgOvm3A=; b=epbCiJ6YRxheqx8g937td3hqaxidha33tM1+7N6rlQKudcIq405Wdtj9yQHgnwt2Bq COLz8Vk9qGnTMyEaxSLaUvkco/Y/W737bIqvJVVY+VMAlG8gyTo96d1kAe+Ghzemz0Iw NBrXKYUYetqy6lJFPXFGbI1kXl4EXOJYFRUQG4kyvnwDOtlpccqQg93bonIexb4GZCEt xdIsuvay/8e1LaofrYcvbXMBlVFm7AidFmAZtcbu5XbtGf1fp1LO8Ozut1U6xAvhyZGC oGPo2HTrjg7cpszK8W1jLQL1vVmcV6jLZPfYL/vjpG2UGnfR10/rXKNfjq/4K6P9F+bY GZZw== X-Gm-Message-State: AOAM531YQ2barhnWE65aXwKgvWWzSvIq8NjKld+gN9b782BI4AMME17U JYzJCXHMWY3Lg8YgI+Ural/ywo3BxyjsR3VNtQ== X-Google-Smtp-Source: ABdhPJy23y6O2GWs1ZzzsznY+2weQGivHo8wFohs3+d56JNy8HS91ZU5gFtXQymzrRP7qF297nODXap5xg/9WnN1VA== X-Received: by 2002:a17:90a:cc18:: with SMTP id b24mr6025997pju.118.1593215751409; Fri, 26 Jun 2020 16:55:51 -0700 (PDT) Date: Fri, 26 Jun 2020 16:55:13 -0700 In-Reply-To: <20200626235519.591734-1-hskinnemoen@google.com> Message-Id: <20200626235519.591734-7-hskinnemoen@google.com> Mime-Version: 1.0 References: <20200626235519.591734-1-hskinnemoen@google.com> X-Mailer: git-send-email 2.27.0.212.ge8ba1cc988-goog Subject: [PATCH v3 06/12] hw/arm: Add two NPCM7xx-based machines From: Havard Skinnemoen To: peter.maydell@linaro.org, clg@kaod.org, joel@jms.id.au Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, Havard Skinnemoen Received-SPF: pass client-ip=2607:f8b0:4864:20::549; envelope-from=3B4v2XgsKCvQdogejjaikajckkcha.Ykimaiq-Zarahjkjcjq.knc@flex--hskinnemoen.bounces.google.com; helo=mail-pg1-x549.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -105 X-Spam_score: -10.6 X-Spam_bar: ---------- X-Spam_report: (-10.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This adds two new machines, both supported by OpenBMC: - npcm750-evb: Nuvoton NPCM750 Evaluation Board. - quanta-gsj: A board with a NPCM730 chip. They rely on the NPCM7xx SoC device to do the heavy lifting. They are almost completely identical at the moment, apart from the SoC type, which currently only changes the reset contents of one register (GCR.MDLR), but they might grow apart a bit more as more functionality is added. Both machines can boot the Linux kernel into /bin/sh. Reviewed-by: Tyrone Ting Reviewed-by: Joel Stanley Reviewed-by: Cédric Le Goater Signed-off-by: Havard Skinnemoen --- hw/arm/Makefile.objs | 2 +- hw/arm/npcm7xx_boards.c | 147 +++++++++++++++++++++++++++++++++++++++ include/hw/arm/npcm7xx.h | 19 +++++ 3 files changed, 167 insertions(+), 1 deletion(-) create mode 100644 hw/arm/npcm7xx_boards.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 13d163a599..c333548ce1 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -41,7 +41,7 @@ obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o obj-$(CONFIG_STM32F405_SOC) += stm32f405_soc.o obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zynqmp.o xlnx-zcu102.o obj-$(CONFIG_XLNX_VERSAL) += xlnx-versal.o xlnx-versal-virt.o -obj-$(CONFIG_NPCM7XX) += npcm7xx.o +obj-$(CONFIG_NPCM7XX) += npcm7xx.o npcm7xx_boards.o obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c new file mode 100644 index 0000000000..c82d9e018b --- /dev/null +++ b/hw/arm/npcm7xx_boards.c @@ -0,0 +1,147 @@ +/* + * Machine definitions for boards featuring an NPCM7xx SoC. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qemu/osdep.h" + +#include "hw/arm/boot.h" +#include "hw/arm/npcm7xx.h" +#include "hw/core/cpu.h" +#include "qapi/error.h" +#include "qemu/units.h" + +#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 +#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff + +static struct arm_boot_info npcm7xx_binfo = { + .loader_start = NPCM7XX_LOADER_START, + .smp_loader_start = NPCM7XX_SMP_LOADER_START, + .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR, + .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR, + .write_secondary_boot = npcm7xx_write_secondary_boot, + .board_id = -1, +}; + +static void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc) +{ + NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc); + + npcm7xx_binfo.ram_size = machine->ram_size; + npcm7xx_binfo.nb_cpus = sc->num_cpus; + + arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo); +} + +static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, + uint32_t hw_straps) +{ + NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine); + NPCM7xxState *soc; + + soc = NPCM7XX(object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", + &error_abort, NULL)); + object_property_set_link(OBJECT(soc), OBJECT(machine->ram), "dram", + &error_abort); + object_property_set_uint(OBJECT(soc), hw_straps, "power-on-straps", + &error_abort); + qdev_realize(DEVICE(soc), NULL, &error_abort); + + return soc; +} + +static void npcm750_evb_init(MachineState *machine) +{ + NPCM7xxState *soc; + + soc = npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS); + + npcm7xx_load_kernel(machine, soc); +} + +static void quanta_gsj_init(MachineState *machine) +{ + NPCM7xxState *soc; + + soc = npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS); + + npcm7xx_load_kernel(machine, soc); +} + +static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *type) +{ + NPCM7xxClass *sc = NPCM7XX_CLASS(object_class_by_name(type)); + MachineClass *mc = MACHINE_CLASS(nmc); + + nmc->soc_type = type; + mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus; +} + +static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->no_floppy = 1; + mc->no_cdrom = 1; + mc->no_parallel = 1; + mc->default_ram_id = "ram"; +} + +/* + * Schematics: + * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-poleg/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf + */ +static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); + MachineClass *mc = MACHINE_CLASS(oc); + + npcm7xx_set_soc_type(nmc, TYPE_NPCM750); + + mc->desc = "Nuvoton NPCM750 Evaluation Board (Cortex A9)"; + mc->init = npcm750_evb_init; + mc->default_ram_size = 512 * MiB; +}; + +static void gsj_machine_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_CLASS(oc); + MachineClass *mc = MACHINE_CLASS(oc); + + npcm7xx_set_soc_type(nmc, TYPE_NPCM730); + + mc->desc = "Quanta GSJ (Cortex A9)"; + mc->init = quanta_gsj_init; + mc->default_ram_size = 512 * MiB; +}; + +static const TypeInfo npcm7xx_machine_types[] = { + { + .name = TYPE_NPCM7XX_MACHINE, + .parent = TYPE_MACHINE, + .instance_size = sizeof(NPCM7xxMachine), + .class_size = sizeof(NPCM7xxMachineClass), + .class_init = npcm7xx_machine_class_init, + .abstract = true, + }, { + .name = MACHINE_TYPE_NAME("npcm750-evb"), + .parent = TYPE_NPCM7XX_MACHINE, + .class_init = npcm750_evb_machine_class_init, + }, { + .name = MACHINE_TYPE_NAME("quanta-gsj"), + .parent = TYPE_NPCM7XX_MACHINE, + .class_init = gsj_machine_class_init, + }, +}; + +DEFINE_TYPES(npcm7xx_machine_types) diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index 38b8c33729..a241af0b8c 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -30,6 +30,25 @@ #define NPCM7XX_SMP_BOOTREG_ADDR (0xF080013C) /* GCR.SCRPAD */ #define NPCM7XX_GIC_CPU_IF_ADDR (0xF03FE100) /* GIC within A9 */ +typedef struct NPCM7xxMachine { + MachineState parent; +} NPCM7xxMachine; + +#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") +#define NPCM7XX_MACHINE(obj) \ + OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) + +typedef struct NPCM7xxMachineClass { + MachineClass parent; + + const char *soc_type; +} NPCM7xxMachineClass; + +#define NPCM7XX_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) +#define NPCM7XX_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) + typedef struct NPCM7xxState { DeviceState parent;