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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:18:56 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans Date: Wed, 22 Jul 2020 17:15:43 +0800 Message-Id: <20200722091641.8834-21-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::542; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x542.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang If SEW < FLEN, call narrower_nanbox_fpr helper to generate the correspond NaN-boxed value. Signed-off-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.inc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 22b4e11a20..85738ba4f7 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2196,7 +2196,18 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc); + if ((s->sew < MO_64 && has_ext(s, RVD)) || + (s->sew < MO_32)) { + /* SEW < FLEN */ + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i32 sew = tcg_const_i32(1 << (s->sew + 3)); + gen_helper_narrower_nanbox_fpr(t1, cpu_fpr[rs1], sew, cpu_env); + fn(dest, mask, t1, src2, cpu_env, desc); + tcg_temp_free_i64(t1); + tcg_temp_free_i32(sew); + } else { + fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc); + } tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask);