[RFC,v2,08/76] target/riscv: rvv-0.9: add mstatus VS field

Message ID	20200722091641.8834-9-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=6956=BB=nongnu.org=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C9E01206D7 From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field Date: Wed, 22 Jul 2020 17:15:31 +0800 Message-Id: <20200722091641.8834-9-frank.chang@sifive.com> In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x444.google.com Precedence: list Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>, Frank Chang <frank.chang@sifive.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: support vector extension v0.9 \| expand [RFC,v2,00/76] target/riscv: support vector extension v0.9 [RFC,v2,01/76] target/riscv: drop vector 0.7.1 support [RFC,v2,02/76] target/riscv: rvv-0.9: support vector 0.9 [RFC,v2,03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion [RFC,v2,04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() [RFC,v2,05/76] target/riscv: fix return value of do_opivx_widen() [RFC,v2,06/76] target/riscv: fix vill bit index in vtype register [RFC,v2,07/76] target/riscv: Use FIELD_EX32() to extract wd field [RFC,v2,08/76] target/riscv: rvv-0.9: add mstatus VS field [RFC,v2,09/76] target/riscv: rvv-0.9: add sstatus VS field [RFC,v2,10/76] target/riscv: rvv-0.9: add translation-time vector context status [RFC,v2,11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register [RFC,v2,12/76] target/riscv: rvv-0.9: add vcsr register [RFC,v2,13/76] target/riscv: rvv-0.9: add vlenb register [RFC,v2,14/76] target/riscv: rvv-0.9: remove MLEN calculations [RFC,v2,15/76] target/riscv: rvv-0.9: add fractional LMUL [RFC,v2,16/76] target/riscv: rvv-0.9: add VMA and VTA [RFC,v2,17/76] target/riscv: rvv-0.9: update check functions [RFC,v2,18/76] target/riscv: introduce more imm value modes in translator functions [RFC,v2,19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper [RFC,v2,20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans [RFC,v2,21/76] target/riscv: rvv-0.9: configure instructions [RFC,v2,22/76] target/riscv: rvv-0.9: stride load and store instructions [RFC,v2,23/76] target/riscv: rvv-0.9: index load and store instructions [RFC,v2,24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns [RFC,v2,25/76] target/riscv: rvv-0.9: fault-only-first unit stride load [RFC,v2,26/76] target/riscv: rvv-0.9: amo operations [RFC,v2,27/76] target/riscv: rvv-0.9: load/store whole register instructions [RFC,v2,28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns [RFC,v2,29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation [RFC,v2,30/76] target/riscv: rvv-0.9: floating-point square-root instruction [RFC,v2,31/76] target/riscv: rvv-0.9: floating-point classify instructions [RFC,v2,32/76] target/riscv: rvv-0.9: mask population count instruction [RFC,v2,33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction [RFC,v2,34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions [RFC,v2,35/76] target/riscv: rvv-0.9: iota instruction [RFC,v2,36/76] target/riscv: rvv-0.9: element index instruction [RFC,v2,37/76] target/riscv: rvv-0.9: allow load element with sign-extended [RFC,v2,38/76] target/riscv: rvv-0.9: register gather instructions [RFC,v2,39/76] target/riscv: rvv-0.9: integer scalar move instructions [RFC,v2,40/76] target/riscv: rvv-0.9: floating-point move instruction [RFC,v2,41/76] target/riscv: rvv-0.9: floating-point scalar move instructions [RFC,v2,42/76] target/riscv: rvv-0.9: whole register move instructions [RFC,v2,43/76] target/riscv: rvv-0.9: integer extension instructions [RFC,v2,44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions [RFC,v2,45/76] target/riscv: rvv-0.9: single-width bit shift instructions [RFC,v2,46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow [RFC,v2,47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions [RFC,v2,48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions [RFC,v2,49/76] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions [RFC,v2,50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions [RFC,v2,51/76] target/riscv: rvv-0.9: integer comparison instructions [RFC,v2,52/76] fpu: implement full set compare for fp16 [RFC,v2,53/76] target/riscv: use softfloat lib float16 comparison functions [RFC,v2,54/76] target/riscv: rvv-0.9: floating-point compare instructions [RFC,v2,55/76] target/riscv: rvv-0.9: single-width integer reduction instructions [RFC,v2,56/76] target/riscv: rvv-0.9: widening integer reduction instructions [RFC,v2,57/76] target/riscv: rvv-0.9: mask-register logical instructions [RFC,v2,58/76] target/riscv: rvv-0.9: slide instructions [RFC,v2,59/76] target/riscv: rvv-0.9: floating-point slide instructions [RFC,v2,60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions [RFC,v2,61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions [RFC,v2,62/76] target/riscv: rvv-0.9: single-width floating-point reduction [RFC,v2,63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions [RFC,v2,64/76] target/riscv: rvv-0.9: single-width scaling shift instructions [RFC,v2,65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add [RFC,v2,66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf [RFC,v2,67/76] target/riscv: rvv-0.9: remove integer extract instruction [RFC,v2,68/76] fpu: add api to handle alternative sNaN propagation [RFC,v2,69/76] target/riscv: rvv-0.9: floating-point min/max instructions [RFC,v2,70/76] softfloat: add fp16 and uint8/int8 interconvert functions [RFC,v2,71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert [RFC,v2,72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert [RFC,v2,73/76] fpu: fix float16 nan check [RFC,v2,74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map [RFC,v2,75/76] target/riscv: gdb: support vector registers for rv64 [RFC,v2,76/76] target/riscv: gdb: support vector registers for rv32

Message ID

20200722091641.8834-9-frank.chang@sifive.com (mailing list archive)

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New, archived

Headers

DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C9E01206D7
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field
Date: Wed, 22 Jul 2020 17:15:31 +0800
Message-Id: <20200722091641.8834-9-frank.chang@sifive.com>
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Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
 Frank Chang <frank.chang@sifive.com>,
 Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
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Series

target/riscv: support vector extension v0.9 | expand

Commit Message

Frank Chang July 22, 2020, 9:15 a.m. UTC

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/cpu.h        |  6 ++++++
 target/riscv/cpu_bits.h   |  1 +
 target/riscv/cpu_helper.c | 16 +++++++++++++++-
 target/riscv/csr.c        | 25 ++++++++++++++++++++++++-
 4 files changed, 46 insertions(+), 2 deletions(-)

Comments

Richard Henderson July 22, 2020, 4:33 p.m. UTC | #1

On 7/22/20 2:15 AM, frank.chang@sifive.com wrote:
> From: LIU Zhiwei <zhiwei_liu@c-sky.com>
> 
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/cpu.h        |  6 ++++++
>  target/riscv/cpu_bits.h   |  1 +
>  target/riscv/cpu_helper.c | 16 +++++++++++++++-
>  target/riscv/csr.c        | 25 ++++++++++++++++++++++++-
>  4 files changed, 46 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 27ce075e50..0a175151da 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -317,6 +317,7 @@  int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
 bool riscv_cpu_fp_enabled(CPURISCVState *env);
+bool riscv_cpu_vector_enabled(CPURISCVState *env);
 bool riscv_cpu_virt_enabled(CPURISCVState *env);
 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
@@ -360,6 +361,7 @@  void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 
 #define TB_FLAGS_MMU_MASK   3
 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
+#define TB_FLAGS_MSTATUS_VS MSTATUS_VS
 
 typedef CPURISCVState CPUArchState;
 typedef RISCVCPU ArchCPU;
@@ -410,11 +412,15 @@  static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
 
 #ifdef CONFIG_USER_ONLY
     flags |= TB_FLAGS_MSTATUS_FS;
+    flags |= TB_FLAGS_MSTATUS_VS;
 #else
     flags |= cpu_mmu_index(env, 0);
     if (riscv_cpu_fp_enabled(env)) {
         flags |= env->mstatus & MSTATUS_FS;
     }
+    if (riscv_cpu_vector_enabled(env)) {
+        flags |= env->mstatus & MSTATUS_VS;
+    }
 #endif
     *pflags = flags;
 }
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8117e8b5a7..a8b3120883 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -367,6 +367,7 @@ 
 #define MSTATUS_SPIE        0x00000020
 #define MSTATUS_MPIE        0x00000080
 #define MSTATUS_SPP         0x00000100
+#define MSTATUS_VS          0x00000600
 #define MSTATUS_MPP         0x00001800
 #define MSTATUS_FS          0x00006000
 #define MSTATUS_XS          0x00018000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 75d2ae3434..3fae736529 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -108,10 +108,24 @@  bool riscv_cpu_fp_enabled(CPURISCVState *env)
     return false;
 }
 
+/* Return true is vector support is currently enabled */
+bool riscv_cpu_vector_enabled(CPURISCVState *env)
+{
+    if (env->mstatus & MSTATUS_VS) {
+        if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) {
+            return false;
+        }
+        return true;
+    }
+
+    return false;
+}
+
 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
 {
     target_ulong mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
-                                MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE;
+                                MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
+                                MSTATUS_VS;
     bool current_virt = riscv_cpu_virt_enabled(env);
 
     g_assert(riscv_has_ext(env, RVH));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ac01c835e1..fb21c87488 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -180,6 +180,7 @@  static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
         return -1;
     }
     env->mstatus |= MSTATUS_FS;
+    env->mstatus |= MSTATUS_VS;
 #endif
     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
     if (vs(env, csrno) >= 0) {
@@ -210,6 +211,13 @@  static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val)
 
 static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val)
 {
+#if !defined(CONFIG_USER_ONLY)
+    if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+        return -1;
+    }
+    env->mstatus |= MSTATUS_VS;
+#endif
+
     env->vxrm = val;
     return 0;
 }
@@ -222,6 +230,13 @@  static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val)
 
 static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val)
 {
+#if !defined(CONFIG_USER_ONLY)
+    if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+        return -1;
+    }
+    env->mstatus |= MSTATUS_VS;
+#endif
+
     env->vxsat = val;
     return 0;
 }
@@ -234,6 +249,13 @@  static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val)
 
 static int write_vstart(CPURISCVState *env, int csrno, target_ulong val)
 {
+#if !defined(CONFIG_USER_ONLY)
+    if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
+        return -1;
+    }
+    env->mstatus |= MSTATUS_VS;
+#endif
+
     env->vstart = val;
     return 0;
 }
@@ -400,7 +422,7 @@  static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
-        MSTATUS_TW;
+        MSTATUS_TW | MSTATUS_VS;
 #if defined(TARGET_RISCV64)
     /*
      * RV32: MPV and MTL are not in mstatus. The current plan is to
@@ -412,6 +434,7 @@  static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
     mstatus = (mstatus & ~mask) | (val & mask);
 
     dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
+            ((mstatus & MSTATUS_VS) == MSTATUS_VS) |
             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
     env->mstatus = mstatus;

[RFC,v2,08/76] target/riscv: rvv-0.9: add mstatus VS field

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