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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id f18sm6567309pgv.84.2020.08.06.03.48.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2020 03:48:35 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v3 30/71] target/riscv: rvv-1.0: mask population count instruction Date: Thu, 6 Aug 2020 18:46:27 +0800 Message-Id: <20200806104709.13235-31-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200806104709.13235-1-frank.chang@sifive.com> References: <20200806104709.13235-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x636.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.inc.c | 7 ++++--- target/riscv/vector_helper.c | 6 +++--- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 25d076d71a8..0a1179370b1 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1066,7 +1066,7 @@ DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32) +DEF_HELPER_4(vpopc_m, tl, ptr, ptr, env, i32) DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index a800c989050..3d2d43ebd8a 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -591,7 +591,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r -vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm +vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 82403dff4b9..e6ec5d24012 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2884,8 +2884,8 @@ GEN_MM_TRANS(vmnor_mm) GEN_MM_TRANS(vmornot_mm) GEN_MM_TRANS(vmxnor_mm) -/* Vector mask population count vmpopc */ -static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) +/* Vector mask population count vpopc */ +static bool trans_vpopc_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s)) { @@ -2904,13 +2904,14 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - gen_helper_vmpopc_m(dst, mask, src2, cpu_env, desc); + gen_helper_vpopc_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(a->rd, dst); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); tcg_temp_free(dst); tcg_temp_free_i32(desc); + return true; } return false; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 77f62c86e02..a18c02eb124 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4465,9 +4465,9 @@ GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR) GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT) GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR) -/* Vector mask population count vmpopc */ -target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env, - uint32_t desc) +/* Vector mask population count vpopc */ +target_ulong HELPER(vpopc_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) { target_ulong cnt = 0; uint32_t vm = vext_vm(desc);