diff mbox series

[RFC,v3,33/71] target/riscv: rvv-1.0: iota instruction

Message ID	20200806104709.13235-34-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=6Y4A=BQ=nongnu.org=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E7EA8204FD From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v3 33/71] target/riscv: rvv-1.0: iota instruction Date: Thu, 6 Aug 2020 18:46:30 +0800 Message-Id: <20200806104709.13235-34-frank.chang@sifive.com> In-Reply-To: <20200806104709.13235-1-frank.chang@sifive.com> References: <20200806104709.13235-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42e.google.com Precedence: list Cc: Frank Chang <frank.chang@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: support vector extension v1.0 \| expand [RFC,v3,00/71] target/riscv: support vector extension v1.0 [RFC,v3,01/71] target/riscv: drop vector 0.7.1 and add 1.0 support [RFC,v3,02/71] target/riscv: Use FIELD_EX32() to extract wd field [RFC,v3,03/71] target/riscv: rvv-1.0: add mstatus VS field [RFC,v3,04/71] target/riscv: rvv-1.0: add sstatus VS field [RFC,v3,05/71] target/riscv: rvv-1.0: introduce writable misa.v field [RFC,v3,06/71] target/riscv: rvv-1.0: add translation-time vector context status [RFC,v3,07/71] target/riscv: rvv-1.0: remove vxrm and vxsat fields from fcsr register [RFC,v3,08/71] target/riscv: rvv-1.0: add vcsr register [RFC,v3,09/71] target/riscv: rvv-1.0: add vlenb register [RFC,v3,10/71] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers [RFC,v3,11/71] target/riscv: rvv-1.0: remove MLEN calculations [RFC,v3,12/71] target/riscv: rvv-1.0: add fractional LMUL [RFC,v3,13/71] target/riscv: rvv-1.0: add VMA and VTA [RFC,v3,14/71] target/riscv: rvv-1.0: update check functions [RFC,v3,15/71] target/riscv: introduce more imm value modes in translator functions [RFC,v3,16/71] target/riscv: add fp16 nan-box check generator function [RFC,v3,17/71] target/riscv: rvv:1.0: add translation-time nan-box helper function [RFC,v3,18/71] target/riscv: rvv-1.0: apply nanbox helper in opfvf_trans [RFC,v3,19/71] target/riscv: rvv-1.0: configure instructions [RFC,v3,20/71] target/riscv: rvv-1.0: stride load and store instructions [RFC,v3,21/71] target/riscv: rvv-1.0: index load and store instructions [RFC,v3,22/71] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns [RFC,v3,23/71] target/riscv: rvv-1.0: fault-only-first unit stride load [RFC,v3,24/71] target/riscv: rvv-1.0: amo operations [RFC,v3,25/71] target/riscv: rvv-1.0: load/store whole register instructions [RFC,v3,26/71] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns [RFC,v3,27/71] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation [RFC,v3,28/71] target/riscv: rvv-1.0: floating-point square-root instruction [RFC,v3,29/71] target/riscv: rvv-1.0: floating-point classify instructions [RFC,v3,30/71] target/riscv: rvv-1.0: mask population count instruction [RFC,v3,31/71] target/riscv: rvv-1.0: find-first-set mask bit instruction [RFC,v3,32/71] target/riscv: rvv-1.0: set-X-first mask bit instructions [RFC,v3,33/71] target/riscv: rvv-1.0: iota instruction [RFC,v3,34/71] target/riscv: rvv-1.0: element index instruction [RFC,v3,35/71] target/riscv: rvv-1.0: allow load element with sign-extended [RFC,v3,36/71] target/riscv: rvv-1.0: register gather instructions [RFC,v3,37/71] target/riscv: rvv-1.0: integer scalar move instructions [RFC,v3,38/71] target/riscv: rvv-1.0: floating-point move instruction [RFC,v3,39/71] target/riscv: rvv-1.0: floating-point scalar move instructions [RFC,v3,40/71] target/riscv: rvv-1.0: whole register move instructions [RFC,v3,41/71] target/riscv: rvv-1.0: integer extension instructions [RFC,v3,42/71] target/riscv: rvv-1.0: single-width averaging add and subtract instructions [RFC,v3,43/71] target/riscv: rvv-1.0: single-width bit shift instructions [RFC,v3,44/71] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow [RFC,v3,45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions [RFC,v3,46/71] target/riscv: rvv-1.0: widening integer multiply-add instructions [RFC,v3,47/71] target/riscv: rvv-1.0: add Zvqmac extension [RFC,v3,48/71] target/riscv: rvv-1.0: quad-widening integer multiply-add instructions [RFC,v3,49/71] target/riscv: rvv-1.0: single-width saturating add and subtract instructions [RFC,v3,50/71] target/riscv: rvv-1.0: integer comparison instructions [RFC,v3,51/71] target/riscv: use softfloat lib float16 comparison functions [RFC,v3,52/71] target/riscv: rvv-1.0: floating-point compare instructions [RFC,v3,53/71] target/riscv: rvv-1.0: mask-register logical instructions [RFC,v3,54/71] target/riscv: rvv-1.0: slide instructions [RFC,v3,55/71] target/riscv: rvv-1.0: floating-point slide instructions [RFC,v3,56/71] target/riscv: rvv-1.0: narrowing fixed-point clip instructions [RFC,v3,57/71] target/riscv: rvv-1.0: single-width floating-point reduction [RFC,v3,58/71] target/riscv: rvv-1.0: widening floating-point reduction instructions [RFC,v3,59/71] target/riscv: rvv-1.0: single-width scaling shift instructions [RFC,v3,60/71] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add [RFC,v3,61/71] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf [RFC,v3,62/71] target/riscv: rvv-1.0: remove integer extract instruction [RFC,v3,63/71] target/riscv: rvv-1.0: floating-point min/max instructions [RFC,v3,64/71] target/riscv: introduce floating-point rounding mode enum [RFC,v3,65/71] target/riscv: rvv-1.0: floating-point/integer type-convert instructions [RFC,v3,66/71] target/riscv: rvv-1.0: widening floating-point/integer type-convert [RFC,v3,67/71] target/riscv: add "set round to odd" rounding mode helper function [RFC,v3,68/71] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert [RFC,v3,69/71] target/riscv: gdb: modify gdb csr xml file to align with csr register map [RFC,v3,70/71] target/riscv: gdb: support vector registers for rv64 [RFC,v3,71/71] target/riscv: gdb: support vector registers for rv32

Commit Message

Frank Chang Aug. 6, 2020, 10:46 a.m. UTC

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn32.decode | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 0992d6ac86d..7a10fc27c5f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -596,7 +596,7 @@  vfirst_m        010000 . ..... 10001 010 ..... 1010111 @r2_vm
 vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
 vmsif_m         010100 . ..... 00011 010 ..... 1010111 @r2_vm
 vmsof_m         010100 . ..... 00010 010 ..... 1010111 @r2_vm
-viota_m         010110 . ..... 10000 010 ..... 1010111 @r2_vm
+viota_m         010100 . ..... 10000 010 ..... 1010111 @r2_vm
 vid_v           010110 . 00000 10001 010 ..... 1010111 @r1_vm
 vext_x_v        001100 1 ..... ..... 010 ..... 1010111 @r
 vmv_s_x         001101 1 00000 ..... 110 ..... 1010111 @r2