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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id f18sm6567309pgv.84.2020.08.06.03.49.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2020 03:49:11 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v3 45/71] target/riscv: rvv-1.0: narrowing integer right shift instructions Date: Thu, 6 Aug 2020 18:46:42 +0800 Message-Id: <20200806104709.13235-46-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200806104709.13235-1-frank.chang@sifive.com> References: <20200806104709.13235-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x631.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/helper.h | 24 ++++++++++---------- target/riscv/insn32.decode | 12 +++++----- target/riscv/insn_trans/trans_rvv.inc.c | 30 ++++++++++++------------- target/riscv/vector_helper.c | 24 ++++++++++---------- 4 files changed, 45 insertions(+), 45 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 3560bf1d4f5..fe37bd2f4af 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -397,18 +397,18 @@ DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32) -DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsra_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsrl_wx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vnsra_wx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vmseq_vv_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmseq_vv_h, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e62bad906a3..c4fe9767585 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -370,12 +370,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm -vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm -vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm -vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm -vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm -vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm -vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm +vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm +vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm +vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm +vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm +vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm +vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 2f5846fe4f0..196f1858465 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1906,7 +1906,7 @@ GEN_OPIVI_GVEC_TRANS(vsrl_vi, IMM_TRUNC_SEW, vsrl_vx, shri) GEN_OPIVI_GVEC_TRANS(vsra_vi, IMM_TRUNC_SEW, vsra_vx, sari) /* Vector Narrowing Integer Right Shift Instructions */ -static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) +static bool opiwv_narrow_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && @@ -1914,10 +1914,10 @@ static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a) } /* OPIVV with NARROW */ -#define GEN_OPIVV_NARROW_TRANS(NAME) \ +#define GEN_OPIWV_NARROW_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivv_narrow_check(s, a)) { \ + if (opiwv_narrow_check(s, a)) { \ uint32_t data = 0; \ static gen_helper_gvec_4_ptr * const fns[3] = { \ gen_helper_##NAME##_b, \ @@ -1939,10 +1939,10 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ } \ return false; \ } -GEN_OPIVV_NARROW_TRANS(vnsra_vv) -GEN_OPIVV_NARROW_TRANS(vnsrl_vv) +GEN_OPIWV_NARROW_TRANS(vnsra_wv) +GEN_OPIWV_NARROW_TRANS(vnsrl_wv) -static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a) +static bool opiwx_narrow_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && vext_check_isa_ill(s) && @@ -1950,10 +1950,10 @@ static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a) } /* OPIVX with NARROW */ -#define GEN_OPIVX_NARROW_TRANS(NAME) \ +#define GEN_OPIWX_NARROW_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivx_narrow_check(s, a)) { \ + if (opiwx_narrow_check(s, a)) { \ static gen_helper_opivx * const fns[3] = { \ gen_helper_##NAME##_b, \ gen_helper_##NAME##_h, \ @@ -1964,14 +1964,14 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ return false; \ } -GEN_OPIVX_NARROW_TRANS(vnsra_vx) -GEN_OPIVX_NARROW_TRANS(vnsrl_vx) +GEN_OPIWX_NARROW_TRANS(vnsra_wx) +GEN_OPIWX_NARROW_TRANS(vnsrl_wx) -/* OPIVI with NARROW */ -#define GEN_OPIVI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \ +/* OPIWI with NARROW */ +#define GEN_OPIWI_NARROW_TRANS(NAME, IMM_MODE, OPIVX) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (opivx_narrow_check(s, a)) { \ + if (opiwx_narrow_check(s, a)) { \ static gen_helper_opivx * const fns[3] = { \ gen_helper_##OPIVX##_b, \ gen_helper_##OPIVX##_h, \ @@ -1983,8 +1983,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ return false; \ } -GEN_OPIVI_NARROW_TRANS(vnsra_vi, IMM_ZX, vnsra_vx) -GEN_OPIVI_NARROW_TRANS(vnsrl_vi, IMM_ZX, vnsrl_vx) +GEN_OPIWI_NARROW_TRANS(vnsra_wi, IMM_ZX, vnsra_wx) +GEN_OPIWI_NARROW_TRANS(vnsrl_wi, IMM_ZX, vnsrl_wx) /* Vector Integer Comparison Instructions */ /* diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index cc501a7cb44..0bed365c8f0 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1395,18 +1395,18 @@ GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f) GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f) /* Vector Narrowing Integer Right Shift Instructions */ -GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) -GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) -GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) -GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf) -GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f) -GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f) -GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) -GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) -GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) -GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf) -GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f) -GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VV(vnsrl_wv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vnsrl_wv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vnsrl_wv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VV(vnsra_wv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VV(vnsra_wv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VV(vnsra_wv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VX(vnsrl_wx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vnsrl_wx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vnsrl_wx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) +GEN_VEXT_SHIFT_VX(vnsra_wx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf) +GEN_VEXT_SHIFT_VX(vnsra_wx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f) +GEN_VEXT_SHIFT_VX(vnsra_wx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f) /* Vector Integer Comparison Instructions */ #define DO_MSEQ(N, M) (N == M)