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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id f18sm6567309pgv.84.2020.08.06.03.50.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2020 03:50:04 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v3 68/71] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert Date: Thu, 6 Aug 2020 18:47:05 +0800 Message-Id: <20200806104709.13235-69-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200806104709.13235-1-frank.chang@sifive.com> References: <20200806104709.13235-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang --- target/riscv/helper.h | 30 ++++++---- target/riscv/insn32.decode | 15 +++-- target/riscv/insn_trans/trans_rvv.inc.c | 52 ++++++++++++++--- target/riscv/vector_helper.c | 76 ++++++++++++++++++------- 4 files changed, 131 insertions(+), 42 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b128610978d..2ecacdc225e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1009,16 +1009,26 @@ DEF_HELPER_5(vfwcvt_rtz_xu_f_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_rtz_x_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_rtz_x_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) -DEF_HELPER_5(vfncvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_xu_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_x_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_x_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_f_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rod_f_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rod_f_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_xu_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_xu_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_xu_f_w_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_x_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_x_f_w_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_rtz_x_f_w_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index fae96194078..3b42cb01a77 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -571,11 +571,16 @@ vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm -vfncvt_xu_f_v 100010 . ..... 10000 001 ..... 1010111 @r2_vm -vfncvt_x_f_v 100010 . ..... 10001 001 ..... 1010111 @r2_vm -vfncvt_f_xu_v 100010 . ..... 10010 001 ..... 1010111 @r2_vm -vfncvt_f_x_v 100010 . ..... 10011 001 ..... 1010111 @r2_vm -vfncvt_f_f_v 100010 . ..... 10100 001 ..... 1010111 @r2_vm + +vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm +vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm +vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm +vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm +vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm +vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm +vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm +vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm + vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 7db3de8e032..080bff45c4f 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2925,7 +2925,7 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) (s->sew != 0); } -#define GEN_OPFV_NARROW_TRANS(NAME) \ +#define GEN_OPFV_NARROW_TRANS(NAME, FRM) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opfv_narrow_check(s, a)) { \ @@ -2935,7 +2935,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, FRM_DYN); \ + gen_set_rm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2950,11 +2950,49 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ return false; \ } -GEN_OPFV_NARROW_TRANS(vfncvt_xu_f_v) -GEN_OPFV_NARROW_TRANS(vfncvt_x_f_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_x_v) -GEN_OPFV_NARROW_TRANS(vfncvt_f_f_v) +GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, FRM_DYN) +GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, FRM_DYN) +GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, FRM_DYN) +GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, FRM_ROD) + +static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + vext_check_isa_ill(s) && + /* OPFV narrowing instructions ignore vs1 check */ + vext_check_sds(s, a->rd, 0, a->rs2, a->vm, false); +} + +#define GEN_OPXFV_NARROW_TRANS(NAME, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opxfv_narrow_check(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + TCGLabel *over = gen_new_label(); \ + gen_set_rm(s, FRM); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w, FRM_DYN) +GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w, FRM_DYN) +GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w, FRM_RTZ) +GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w, FRM_RTZ) /* *** Vector Reduction Operations diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2f5a2dca336..de0c02c3a16 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4131,31 +4131,36 @@ GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8) /* Narrowing Floating-Point/Integer Type-Convert Instructions */ /* (TD, T2, TX2) */ +#define NOP_UU_B uint8_t, uint16_t, uint32_t #define NOP_UU_H uint16_t, uint32_t, uint32_t #define NOP_UU_W uint32_t, uint64_t, uint64_t /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ -RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16) -RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32) -GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2) -GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4) +RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8) +RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16) +RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1, 1) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4, 4) /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */ -RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16) -RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32) -GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2) -GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4) +RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8) +RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16) +RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32) +GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1, 1) +GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4, 4) /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */ -RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16) -RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2) -GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4) +RVVCALL(OPFVV1, vfncvt_f_xu_w_h, NOP_UU_H, H2, H4, uint32_to_float16) +RVVCALL(OPFVV1, vfncvt_f_xu_w_w, NOP_UU_W, H4, H8, uint64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_xu_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_xu_w_w, 4, 4) /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */ -RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16) -RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2) -GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4) +RVVCALL(OPFVV1, vfncvt_f_x_w_h, NOP_UU_H, H2, H4, int32_to_float16) +RVVCALL(OPFVV1, vfncvt_f_x_w_w, NOP_UU_W, H4, H8, int64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_x_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_x_w_w, 4, 4) /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */ static uint16_t vfncvtffv16(uint32_t a, float_status *s) @@ -4163,10 +4168,41 @@ static uint16_t vfncvtffv16(uint32_t a, float_status *s) return float32_to_float16(a, true, s); } -RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16) -RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32) -GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2) -GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4) +RVVCALL(OPFVV1, vfncvt_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16) +RVVCALL(OPFVV1, vfncvt_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32) +GEN_VEXT_V_ENV(vfncvt_f_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_f_f_w_w, 4, 4) + +/* + * vfncvt.rod.f.f.w vd, vs2, vm + * Convert double-width float to single-width float, rounding towards odd. + */ +RVVCALL(OPFVV1, vfncvt_rod_f_f_w_h, NOP_UU_H, H2, H4, vfncvtffv16) +RVVCALL(OPFVV1, vfncvt_rod_f_f_w_w, NOP_UU_W, H4, H8, float64_to_float32) +GEN_VEXT_V_ENV(vfncvt_rod_f_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_rod_f_f_w_w, 4, 4) + +/* + * vfncvt.rtz.xu.f.w vd, vs2, vm + * Convert double-width float to unsigned integer, truncating. + */ +RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8) +RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16) +RVVCALL(OPFVV1, vfncvt_rtz_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32) +GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_b, 1, 1) +GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_rtz_xu_f_w_w, 4, 4) + +/* + * vfncvt.rtz.x.f.w vd, vs2, vm + * Convert double-width float to signed integer, truncating. + */ +RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8) +RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16) +RVVCALL(OPFVV1, vfncvt_rtz_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32) +GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_b, 1, 1) +GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_h, 2, 2) +GEN_VEXT_V_ENV(vfncvt_rtz_x_f_w_w, 4, 4) /* *** Vector Reduction Operations