From patchwork Wed Dec 2 19:04:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 11946853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C163BC71156 for ; Wed, 2 Dec 2020 19:06:51 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DF99822254 for ; Wed, 2 Dec 2020 19:06:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DF99822254 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csgraf.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kkXSj-0005Ox-AB for qemu-devel@archiver.kernel.org; Wed, 02 Dec 2020 14:06:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58908) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kkXQT-0003L5-VP; Wed, 02 Dec 2020 14:04:29 -0500 Received: from mail.csgraf.de ([188.138.100.120]:56516 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kkXQO-0005Hb-5m; Wed, 02 Dec 2020 14:04:29 -0500 Received: from localhost.localdomain (dynamic-077-007-031-140.77.7.pool.telefonica.de [77.7.31.140]) by csgraf.de (Postfix) with ESMTPSA id A173939004F5; Wed, 2 Dec 2020 20:04:19 +0100 (CET) From: Alexander Graf To: qemu-devel@nongnu.org Subject: [PATCH v3 09/10] hvf: arm: Add support for GICv3 Date: Wed, 2 Dec 2020 20:04:07 +0100 Message-Id: <20201202190408.2041-10-agraf@csgraf.de> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20201202190408.2041-1-agraf@csgraf.de> References: <20201202190408.2041-1-agraf@csgraf.de> MIME-Version: 1.0 Received-SPF: pass client-ip=188.138.100.120; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , Richard Henderson , Cameron Esfahani , Roman Bolshakov , qemu-arm@nongnu.org, Frank Yang , Paolo Bonzini , Peter Collingbourne Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We currently only support GICv2 emulation. To also support GICv3, we will need to pass a few system registers into their respective handler functions. This patch adds handling for all of the required system registers, so that we can run with more than 8 vCPUs. Signed-off-by: Alexander Graf --- target/arm/hvf/hvf.c | 141 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 79aeeb237b..dfdf0827e4 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -23,6 +23,7 @@ #include "exec/address-spaces.h" #include "hw/irq.h" +#include "hw/intc/gicv3_internal.h" #include "qemu/main-loop.h" #include "sysemu/accel.h" #include "sysemu/cpus.h" @@ -47,6 +48,33 @@ #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 1, 14, 0) #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 0, 9, 13) +#define SYSREG_ICC_AP0R0_EL1 SYSREG(3, 0, 4, 12, 8) +#define SYSREG_ICC_AP0R1_EL1 SYSREG(3, 0, 5, 12, 8) +#define SYSREG_ICC_AP0R2_EL1 SYSREG(3, 0, 6, 12, 8) +#define SYSREG_ICC_AP0R3_EL1 SYSREG(3, 0, 7, 12, 8) +#define SYSREG_ICC_AP1R0_EL1 SYSREG(3, 0, 0, 12, 9) +#define SYSREG_ICC_AP1R1_EL1 SYSREG(3, 0, 1, 12, 9) +#define SYSREG_ICC_AP1R2_EL1 SYSREG(3, 0, 2, 12, 9) +#define SYSREG_ICC_AP1R3_EL1 SYSREG(3, 0, 3, 12, 9) +#define SYSREG_ICC_ASGI1R_EL1 SYSREG(3, 0, 6, 12, 11) +#define SYSREG_ICC_BPR0_EL1 SYSREG(3, 0, 3, 12, 8) +#define SYSREG_ICC_BPR1_EL1 SYSREG(3, 0, 3, 12, 12) +#define SYSREG_ICC_CTLR_EL1 SYSREG(3, 0, 4, 12, 12) +#define SYSREG_ICC_DIR_EL1 SYSREG(3, 0, 1, 12, 11) +#define SYSREG_ICC_EOIR0_EL1 SYSREG(3, 0, 1, 12, 8) +#define SYSREG_ICC_EOIR1_EL1 SYSREG(3, 0, 1, 12, 12) +#define SYSREG_ICC_HPPIR0_EL1 SYSREG(3, 0, 2, 12, 8) +#define SYSREG_ICC_HPPIR1_EL1 SYSREG(3, 0, 2, 12, 12) +#define SYSREG_ICC_IAR0_EL1 SYSREG(3, 0, 0, 12, 8) +#define SYSREG_ICC_IAR1_EL1 SYSREG(3, 0, 0, 12, 12) +#define SYSREG_ICC_IGRPEN0_EL1 SYSREG(3, 0, 6, 12, 12) +#define SYSREG_ICC_IGRPEN1_EL1 SYSREG(3, 0, 7, 12, 12) +#define SYSREG_ICC_PMR_EL1 SYSREG(3, 0, 0, 4, 6) +#define SYSREG_ICC_RPR_EL1 SYSREG(3, 0, 3, 12, 11) +#define SYSREG_ICC_SGI0R_EL1 SYSREG(3, 0, 7, 12, 11) +#define SYSREG_ICC_SGI1R_EL1 SYSREG(3, 0, 5, 12, 11) +#define SYSREG_ICC_SRE_EL1 SYSREG(3, 0, 5, 12, 12) + #define WFX_IS_WFE (1 << 0) struct hvf_reg_match { @@ -419,6 +447,38 @@ void hvf_kick_vcpu_thread(CPUState *cpu) hv_vcpus_exit(&cpu->hvf->fd, 1); } +static uint32_t hvf_reg2cp_reg(uint32_t reg) +{ + return ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, + (reg >> 10) & 0xf, + (reg >> 1) & 0xf, + (reg >> 20) & 0x3, + (reg >> 14) & 0x7, + (reg >> 17) & 0x7); +} + +static uint64_t hvf_sysreg_read_cp(CPUState *cpu, uint32_t reg) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + const ARMCPRegInfo *ri; + uint64_t val = 0; + + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); + if (ri) { + if (ri->type & ARM_CP_CONST) { + val = ri->resetvalue; + } else if (ri->readfn) { + val = ri->readfn(env, ri); + } else { + val = CPREG_FIELD64(env, ri); + } + DPRINTF("vgic read from %s [val=%016llx]", ri->name, val); + } + + return val; +} + static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -432,6 +492,39 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) case SYSREG_PMCCNTR_EL0: val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); break; + case SYSREG_ICC_AP0R0_EL1: + case SYSREG_ICC_AP0R1_EL1: + case SYSREG_ICC_AP0R2_EL1: + case SYSREG_ICC_AP0R3_EL1: + case SYSREG_ICC_AP1R0_EL1: + case SYSREG_ICC_AP1R1_EL1: + case SYSREG_ICC_AP1R2_EL1: + case SYSREG_ICC_AP1R3_EL1: + case SYSREG_ICC_ASGI1R_EL1: + case SYSREG_ICC_BPR0_EL1: + case SYSREG_ICC_BPR1_EL1: + case SYSREG_ICC_DIR_EL1: + case SYSREG_ICC_EOIR0_EL1: + case SYSREG_ICC_EOIR1_EL1: + case SYSREG_ICC_HPPIR0_EL1: + case SYSREG_ICC_HPPIR1_EL1: + case SYSREG_ICC_IAR0_EL1: + case SYSREG_ICC_IAR1_EL1: + case SYSREG_ICC_IGRPEN0_EL1: + case SYSREG_ICC_IGRPEN1_EL1: + case SYSREG_ICC_PMR_EL1: + case SYSREG_ICC_SGI0R_EL1: + case SYSREG_ICC_SGI1R_EL1: + case SYSREG_ICC_SRE_EL1: + val = hvf_sysreg_read_cp(cpu, reg); + break; + case SYSREG_ICC_CTLR_EL1: + val = hvf_sysreg_read_cp(cpu, reg); + + /* AP0R registers above 0 don't trap, expose less PRIs to fit */ + val &= ~ICC_CTLR_EL1_PRIBITS_MASK; + val |= 4 << ICC_CTLR_EL1_PRIBITS_SHIFT; + break; default: DPRINTF("unhandled sysreg read %08x (op0=%d op1=%d op2=%d " "crn=%d crm=%d)", reg, (reg >> 20) & 0x3, @@ -443,6 +536,24 @@ static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg) return val; } +static void hvf_sysreg_write_cp(CPUState *cpu, uint32_t reg, uint64_t val) +{ + ARMCPU *arm_cpu = ARM_CPU(cpu); + CPUARMState *env = &arm_cpu->env; + const ARMCPRegInfo *ri; + + ri = get_arm_cp_reginfo(arm_cpu->cp_regs, hvf_reg2cp_reg(reg)); + + if (ri) { + if (ri->writefn) { + ri->writefn(env, ri, val); + } else { + CPREG_FIELD64(env, ri) = val; + } + DPRINTF("vgic write to %s [val=%016llx]", ri->name, val); + } +} + static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -450,6 +561,36 @@ static void hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val) switch (reg) { case SYSREG_CNTPCT_EL0: break; + case SYSREG_ICC_AP0R0_EL1: + case SYSREG_ICC_AP0R1_EL1: + case SYSREG_ICC_AP0R2_EL1: + case SYSREG_ICC_AP0R3_EL1: + case SYSREG_ICC_AP1R0_EL1: + case SYSREG_ICC_AP1R1_EL1: + case SYSREG_ICC_AP1R2_EL1: + case SYSREG_ICC_AP1R3_EL1: + case SYSREG_ICC_ASGI1R_EL1: + case SYSREG_ICC_BPR0_EL1: + case SYSREG_ICC_BPR1_EL1: + case SYSREG_ICC_CTLR_EL1: + case SYSREG_ICC_DIR_EL1: + case SYSREG_ICC_HPPIR0_EL1: + case SYSREG_ICC_HPPIR1_EL1: + case SYSREG_ICC_IAR0_EL1: + case SYSREG_ICC_IAR1_EL1: + case SYSREG_ICC_IGRPEN0_EL1: + case SYSREG_ICC_IGRPEN1_EL1: + case SYSREG_ICC_PMR_EL1: + case SYSREG_ICC_SGI0R_EL1: + case SYSREG_ICC_SGI1R_EL1: + case SYSREG_ICC_SRE_EL1: + hvf_sysreg_write_cp(cpu, reg, val); + break; + case SYSREG_ICC_EOIR0_EL1: + case SYSREG_ICC_EOIR1_EL1: + hvf_sysreg_write_cp(cpu, reg, val); + qemu_set_irq(arm_cpu->gt_timer_outputs[GTIMER_VIRT], 0); + hv_vcpu_set_vtimer_mask(cpu->hvf->fd, false); default: DPRINTF("unhandled sysreg write %08x", reg); break;