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Fri, 15 Jan 2021 04:06:22 -0800 (PST) Received: from localhost.localdomain ([211.108.35.36]) by smtp.gmail.com with ESMTPSA id a4sm8338161pgn.40.2021.01.15.04.06.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Jan 2021 04:06:21 -0800 (PST) From: Minwoo Im To: qemu-devel@nongnu.org, qemu-block@nongnu.org Subject: [RFC PATCH 3/5] hw/block/nvme: add multi-controller param for mpath Date: Fri, 15 Jan 2021 21:05:56 +0900 Message-Id: <20210115120558.29313-4-minwoo.im.dev@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210115120558.29313-1-minwoo.im.dev@gmail.com> References: <20210115120558.29313-1-minwoo.im.dev@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=minwoo.im.dev@gmail.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Keith Busch , Klaus Jensen , Minwoo Im , Kevin Wolf , Max Reitz Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Added mpath.ctrl parameter to set multi-controller bit[1] in CMIC field in Identify Controller data structure. It will indicate that a NVM subsystem can have two or more controllers in the subsystem. To set up multi-controller in a NVM subsystem, user needs to give same serial parameter to the controllers (-device), but different cntlid parameter to each controllers (-device). Example: -device nvme,ctrlid=0,serial=foo,... -device nvme,ctrlid=1,serial=foo,... The example above prepares two different controllers in a NVM subsystem with the same serial which leads to same subsystem NQN. Signed-off-by: Minwoo Im --- hw/block/nvme.c | 10 ++++++++++ hw/block/nvme.h | 1 + 2 files changed, 11 insertions(+) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 132e61c0ee7b..50b349cf9ea3 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -57,6 +57,11 @@ * This value will be reported through Identify Controller data structure * with a field named CNTLID[79:78]. * + * - `mpath.ctrl` + * Multi-path I/O with multi-controller (default: false). A NVM subsystem + * can hold two or more controllers. This will be reflected to Identify + * Controller data structure CMIC[76] field. + * * - `zoned.append_size_limit` * The maximum I/O size in bytes that is allowed in Zone Append command. * The default is 128KiB. Since internally this this value is maintained as @@ -4284,6 +4289,10 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev) n->bar.intmc = n->bar.intms = 0; id->cntlid = n->params.cntlid; + + if (n->params.mpath_ctrl) { + id->cmic |= NVME_CMIC_MULTI_CTRL; + } } static void nvme_realize(PCIDevice *pci_dev, Error **errp) @@ -4364,6 +4373,7 @@ static Property nvme_props[] = { DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64), DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7), DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false), + DEFINE_PROP_BOOL("mpath.ctrl", NvmeCtrl, params.mpath_ctrl, false), DEFINE_PROP_SIZE32("zoned.append_size_limit", NvmeCtrl, params.zasl_bs, NVME_DEFAULT_MAX_ZA_SIZE), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 6aa9e89ac5a8..73c9c2cff247 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -21,6 +21,7 @@ typedef struct NvmeParams { uint8_t mdts; bool use_intel_id; uint32_t zasl_bs; + bool mpath_ctrl; } NvmeParams; typedef struct NvmeAsyncEvent {