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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id a30sm1833344lfo.56.2021.02.22.00.33.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 00:33:26 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PULL v1 1/3] target/cris: Use MMUAccessType enum type when possible Date: Mon, 22 Feb 2021 09:33:22 +0100 Message-Id: <20210222083324.331908-2-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210222083324.331908-1-edgar.iglesias@gmail.com> References: <20210222083324.331908-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::232; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, f4bug@amsat.org, stefans@axis.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé Replace the 0/1/2 magic values by the corresponding MMUAccessType. We can remove a comment as enum names are self explicit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Message-Id: <20210128003223.3561108-2-f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias --- target/cris/helper.c | 4 ++-- target/cris/mmu.c | 13 ++++++------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/cris/helper.c b/target/cris/helper.c index 7e3bb58fe1..911867f3b4 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -275,10 +275,10 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) struct cris_mmu_result res; int miss; - miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1); + miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_DATA_LOAD, 0, 1); /* If D TLB misses, try I TLB. */ if (miss) { - miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1); + miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_INST_FETCH, 0, 1); } if (!miss) { diff --git a/target/cris/mmu.c b/target/cris/mmu.c index a279b7f1b6..294de7dffd 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -152,15 +152,15 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, pid = env->pregs[PR_PID] & 0xff; switch (rw) { - case 2: + case MMU_INST_FETCH: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break; - case 1: + case MMU_DATA_STORE: rwcause = CRIS_MMU_ERR_WRITE; break; default: - case 0: + case MMU_DATA_LOAD: rwcause = CRIS_MMU_ERR_READ; break; } @@ -219,13 +219,13 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, vaddr, lo, env->pc)); match = 0; res->bf_vec = vect_base + 2; - } else if (rw == 1 && cfg_w && !tlb_w) { + } else if (rw == MMU_DATA_STORE && cfg_w && !tlb_w) { D(printf("tlb: write protected %x lo=%x pc=%x\n", vaddr, lo, env->pc)); match = 0; /* write accesses never go through the I mmu. */ res->bf_vec = vect_base + 3; - } else if (rw == 2 && cfg_x && !tlb_x) { + } else if (rw == MMU_INST_FETCH && cfg_x && !tlb_x) { D(printf("tlb: exec protected %x lo=%x pc=%x\n", vaddr, lo, env->pc)); match = 0; @@ -329,8 +329,7 @@ int cris_mmu_translate(struct cris_mmu_result *res, old_srs = env->pregs[PR_SRS]; - /* rw == 2 means exec, map the access to the insn mmu. */ - env->pregs[PR_SRS] = rw == 2 ? 1 : 2; + env->pregs[PR_SRS] = rw == MMU_INST_FETCH ? 1 : 2; if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) { res->phy = vaddr;