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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id f13sm2036378ljo.39.2021.02.22.00.33.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 00:33:27 -0800 (PST) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PULL v1 2/3] target/cris: Let cris_mmu_translate() use MMUAccessType access_type Date: Mon, 22 Feb 2021 09:33:23 +0100 Message-Id: <20210222083324.331908-3-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210222083324.331908-1-edgar.iglesias@gmail.com> References: <20210222083324.331908-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, f4bug@amsat.org, stefans@axis.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Philippe Mathieu-Daudé All callers of cris_mmu_translate() provide a MMUAccessType type. Let the prototype use it as argument, as it is stricter than an integer. We can remove the documentation as enum names are self explicit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias Message-Id: <20210128003223.3561108-3-f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias --- target/cris/mmu.h | 2 +- target/cris/mmu.c | 24 ++++++++++++------------ 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/cris/mmu.h b/target/cris/mmu.h index 9ab1642b96..d57386ec6c 100644 --- a/target/cris/mmu.h +++ b/target/cris/mmu.h @@ -17,6 +17,6 @@ void cris_mmu_init(CPUCRISState *env); void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid); int cris_mmu_translate(struct cris_mmu_result *res, CPUCRISState *env, uint32_t vaddr, - int rw, int mmu_idx, int debug); + MMUAccessType access_type, int mmu_idx, int debug); #endif diff --git a/target/cris/mmu.c b/target/cris/mmu.c index 294de7dffd..b574ec6e5b 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -129,10 +129,10 @@ static void dump_tlb(CPUCRISState *env, int mmu) } #endif -/* rw 0 = read, 1 = write, 2 = exec. */ static int cris_mmu_translate_page(struct cris_mmu_result *res, - CPUCRISState *env, uint32_t vaddr, - int rw, int usermode, int debug) + CPUCRISState *env, uint32_t vaddr, + MMUAccessType access_type, + int usermode, int debug) { unsigned int vpage; unsigned int idx; @@ -151,7 +151,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, r_cfg = env->sregs[SFR_RW_MM_CFG]; pid = env->pregs[PR_PID] & 0xff; - switch (rw) { + switch (access_type) { case MMU_INST_FETCH: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; @@ -219,13 +219,13 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, vaddr, lo, env->pc)); match = 0; res->bf_vec = vect_base + 2; - } else if (rw == MMU_DATA_STORE && cfg_w && !tlb_w) { + } else if (access_type == MMU_DATA_STORE && cfg_w && !tlb_w) { D(printf("tlb: write protected %x lo=%x pc=%x\n", vaddr, lo, env->pc)); match = 0; /* write accesses never go through the I mmu. */ res->bf_vec = vect_base + 3; - } else if (rw == MMU_INST_FETCH && cfg_x && !tlb_x) { + } else if (access_type == MMU_INST_FETCH && cfg_x && !tlb_x) { D(printf("tlb: exec protected %x lo=%x pc=%x\n", vaddr, lo, env->pc)); match = 0; @@ -272,9 +272,9 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc)); } - D(printf("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x" + D(printf("%s access=%u mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x" " %x cause=%x sel=%x sp=%x %x %x\n", - __func__, rw, match, env->pc, + __func__, access_type, match, env->pc, vaddr, vpage, tlb_vpn, tlb_pfn, tlb_pid, pid, @@ -319,8 +319,8 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) } int cris_mmu_translate(struct cris_mmu_result *res, - CPUCRISState *env, uint32_t vaddr, - int rw, int mmu_idx, int debug) + CPUCRISState *env, uint32_t vaddr, + MMUAccessType access_type, int mmu_idx, int debug) { int seg; int miss = 0; @@ -329,7 +329,7 @@ int cris_mmu_translate(struct cris_mmu_result *res, old_srs = env->pregs[PR_SRS]; - env->pregs[PR_SRS] = rw == MMU_INST_FETCH ? 1 : 2; + env->pregs[PR_SRS] = access_type == MMU_INST_FETCH ? 1 : 2; if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) { res->phy = vaddr; @@ -346,7 +346,7 @@ int cris_mmu_translate(struct cris_mmu_result *res, res->phy = base | (0x0fffffff & vaddr); res->prot = PAGE_BITS; } else { - miss = cris_mmu_translate_page(res, env, vaddr, rw, + miss = cris_mmu_translate_page(res, env, vaddr, access_type, is_user, debug); } done: