diff mbox series

[v5,2/4] target/arm: Make sure that commpage's tb->size != 0

Message ID 20210416154939.32404-3-iii@linux.ibm.com (mailing list archive)
State New, archived
Headers show
Series accel/tcg: Make sure that tb->size != 0 after translation | expand

Commit Message

Ilya Leoshkevich April 16, 2021, 3:49 p.m. UTC 
tb_gen_code() assumes that tb->size must never be zero, otherwise it
may produce spurious exceptions. For ARM this may happen when creating
a translation block for the commpage.

Fix by pretending that commpage translation blocks have at least one
instruction.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
 target/arm/translate.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Richard Henderson April 23, 2021, 5:49 p.m. UTC | #1 
On 4/16/21 8:49 AM, Ilya Leoshkevich wrote:
> tb_gen_code() assumes that tb->size must never be zero, otherwise it
> may produce spurious exceptions. For ARM this may happen when creating
> a translation block for the commpage.
> 
> Fix by pretending that commpage translation blocks have at least one
> instruction.
> 
> Signed-off-by: Ilya Leoshkevich<iii@linux.ibm.com>
> ---
>   target/arm/translate.c | 2 ++
>   1 file changed, 2 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 62b1c2081b..cb9e30c341 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9060,6 +9060,7 @@  static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     unsigned int insn;
 
     if (arm_pre_translate_insn(dc)) {
+        dc->base.pc_next += 4;
         return;
     }
 
@@ -9129,6 +9130,7 @@  static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
     bool is_16bit;
 
     if (arm_pre_translate_insn(dc)) {
+        dc->base.pc_next += 2;
         return;
     }