@@ -1079,8 +1079,8 @@ static void arm_cpu_initfn(Object *obj)
cpu->psci_version = 1; /* By default assume PSCI v0.1 */
cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
- if (tcg_enabled()) {
- cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
+ if (tcg_enabled() || hvf_enabled()) {
+ cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */
}
}
@@ -25,6 +25,7 @@
#include "hw/irq.h"
#include "qemu/main-loop.h"
#include "sysemu/cpus.h"
+#include "arm-powerctl.h"
#include "target/arm/cpu.h"
#include "target/arm/internals.h"
#include "trace/trace-target_arm_hvf.h"
@@ -45,6 +46,8 @@
#define TMR_CTL_IMASK (1 << 1)
#define TMR_CTL_ISTATUS (1 << 2)
+static void hvf_wfi(CPUState *cpu);
+
typedef struct ARMHostCPUFeatures {
ARMISARegisters isar;
uint64_t features;
@@ -551,6 +554,109 @@ static void hvf_raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndro
env->pc = addr;
}
+static int hvf_psci_cpu_off(ARMCPU *arm_cpu)
+{
+ int32_t ret = 0;
+ ret = arm_set_cpu_off(arm_cpu->mp_affinity);
+ assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS);
+
+ return 0;
+}
+
+static int hvf_handle_psci_call(CPUState *cpu)
+{
+ ARMCPU *arm_cpu = ARM_CPU(cpu);
+ CPUARMState *env = &arm_cpu->env;
+ uint64_t param[4] = {
+ env->xregs[0],
+ env->xregs[1],
+ env->xregs[2],
+ env->xregs[3]
+ };
+ uint64_t context_id, mpidr;
+ bool target_aarch64 = true;
+ CPUState *target_cpu_state;
+ ARMCPU *target_cpu;
+ target_ulong entry;
+ int target_el = 1;
+ int32_t ret = 0;
+
+ trace_hvf_psci_call(param[0], param[1], param[2], param[3], arm_cpu->mp_affinity);
+
+ switch (param[0]) {
+ case QEMU_PSCI_0_2_FN_PSCI_VERSION:
+ ret = QEMU_PSCI_0_2_RET_VERSION_0_2;
+ break;
+ case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
+ ret = QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED; /* No trusted OS */
+ break;
+ case QEMU_PSCI_0_2_FN_AFFINITY_INFO:
+ case QEMU_PSCI_0_2_FN64_AFFINITY_INFO:
+ mpidr = param[1];
+
+ switch (param[2]) {
+ case 0:
+ target_cpu_state = arm_get_cpu_by_id(mpidr);
+ if (!target_cpu_state) {
+ ret = QEMU_PSCI_RET_INVALID_PARAMS;
+ break;
+ }
+ target_cpu = ARM_CPU(target_cpu_state);
+
+ ret = target_cpu->power_state;
+ break;
+ default:
+ /* Everything above affinity level 0 is always on. */
+ ret = 0;
+ }
+ break;
+ case QEMU_PSCI_0_2_FN_SYSTEM_RESET:
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ /* QEMU reset and shutdown are async requests, but PSCI
+ * mandates that we never return from the reset/shutdown
+ * call, so power the CPU off now so it doesn't execute
+ * anything further.
+ */
+ return hvf_psci_cpu_off(arm_cpu);
+ case QEMU_PSCI_0_2_FN_SYSTEM_OFF:
+ qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
+ return hvf_psci_cpu_off(arm_cpu);
+ case QEMU_PSCI_0_1_FN_CPU_ON:
+ case QEMU_PSCI_0_2_FN_CPU_ON:
+ case QEMU_PSCI_0_2_FN64_CPU_ON:
+ mpidr = param[1];
+ entry = param[2];
+ context_id = param[3];
+ ret = arm_set_cpu_on(mpidr, entry, context_id,
+ target_el, target_aarch64);
+ break;
+ case QEMU_PSCI_0_1_FN_CPU_OFF:
+ case QEMU_PSCI_0_2_FN_CPU_OFF:
+ return hvf_psci_cpu_off(arm_cpu);
+ case QEMU_PSCI_0_1_FN_CPU_SUSPEND:
+ case QEMU_PSCI_0_2_FN_CPU_SUSPEND:
+ case QEMU_PSCI_0_2_FN64_CPU_SUSPEND:
+ /* Affinity levels are not supported in QEMU */
+ if (param[1] & 0xfffe0000) {
+ ret = QEMU_PSCI_RET_INVALID_PARAMS;
+ break;
+ }
+ /* Powerdown is not supported, we always go into WFI */
+ env->xregs[0] = 0;
+ hvf_wfi(cpu);
+ break;
+ case QEMU_PSCI_0_1_FN_MIGRATE:
+ case QEMU_PSCI_0_2_FN_MIGRATE:
+ ret = QEMU_PSCI_RET_NOT_SUPPORTED;
+ break;
+ default:
+ return 1;
+ }
+
+ env->xregs[0] = ret;
+ return 0;
+}
+
static uint64_t hvf_sysreg_read(CPUState *cpu, uint32_t reg)
{
ARMCPU *arm_cpu = ARM_CPU(cpu);
@@ -712,6 +818,8 @@ int hvf_vcpu_exec(CPUState *cpu)
}
if (cpu->halted) {
+ /* On unhalt, we usually have CPU state changes. Prepare for them. */
+ cpu_synchronize_state(cpu);
return EXCP_HLT;
}
@@ -809,13 +917,21 @@ int hvf_vcpu_exec(CPUState *cpu)
break;
case EC_AA64_HVC:
cpu_synchronize_state(cpu);
- trace_hvf_unknown_hvf(env->xregs[0]);
- hvf_raise_exception(env, EXCP_UDEF, syn_uncategorized());
+ if (!hvf_handle_psci_call(cpu)) {
+ advance_pc = true;
+ } else {
+ trace_hvf_unknown_hvf(env->xregs[0]);
+ hvf_raise_exception(env, EXCP_UDEF, syn_uncategorized());
+ }
break;
case EC_AA64_SMC:
cpu_synchronize_state(cpu);
- trace_hvf_unknown_smc(env->xregs[0]);
- hvf_raise_exception(env, EXCP_UDEF, syn_uncategorized());
+ if (!hvf_handle_psci_call(cpu)) {
+ advance_pc = true;
+ } else {
+ trace_hvf_unknown_smc(env->xregs[0]);
+ hvf_raise_exception(env, EXCP_UDEF, syn_uncategorized());
+ }
break;
default:
cpu_synchronize_state(cpu);
@@ -8,3 +8,4 @@ hvf_sysreg_write(uint32_t reg, uint32_t op0, uint32_t op1, uint32_t crn, uint32_
hvf_unknown_hvf(uint64_t x0) "unknown HVC! %016"PRIx64
hvf_unknown_smc(uint64_t x0) "unknown SMC! %016"PRIx64
hvf_exit(uint64_t syndrome, uint32_t ec, uint64_t pc) "exit: 0x%"PRIx64" [ec=0x%x pc=0x%"PRIx64"]"
+hvf_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t cpuid) "PSCI Call x0=%016"PRIx64" x1=%016"PRIx64" x2=%016"PRIx64" x3=%016"PRIx64" cpu=%x"
We need to handle PSCI calls. Most of the TCG code works for us, but we can simplify it to only handle aa64 mode and we need to handle SUSPEND differently. This patch takes the TCG code as template and duplicates it in HVF. To tell the guest that we support PSCI 0.2 now, update the check in arm_cpu_initfn() as well. Signed-off-by: Alexander Graf <agraf@csgraf.de> --- v6 -> v7: - This patch integrates "arm: Set PSCI to 0.2 for HVF" --- target/arm/cpu.c | 4 +- target/arm/hvf/hvf.c | 124 ++++++++++++++++++++++++++++++++++-- target/arm/hvf/trace-events | 1 + 3 files changed, 123 insertions(+), 6 deletions(-)