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Thu, 20 May 2021 10:56:52 -0400 (EDT) Received: from localhost (disaster-area.hh.sledj.net [local]) by disaster-area.hh.sledj.net (OpenSMTPD) with ESMTPA id 0c7b4072; Thu, 20 May 2021 14:56:48 +0000 (UTC) From: David Edmondson To: qemu-devel@nongnu.org Subject: [RFC PATCH 5/7] target/i386: Introduce AMD X86XSaveArea sub-union Date: Thu, 20 May 2021 15:56:45 +0100 Message-Id: <20210520145647.3483809-6-david.edmondson@oracle.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210520145647.3483809-1-david.edmondson@oracle.com> References: <20210520145647.3483809-1-david.edmondson@oracle.com> MIME-Version: 1.0 Received-SPF: softfail client-ip=66.111.4.223; envelope-from=david.edmondson@oracle.com; helo=forward1-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Richard Henderson , David Edmondson , Babu Moger , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" AMD stores the pkru_state at a different offset to Intel. Signed-off-by: David Edmondson --- target/i386/cpu.h | 17 +++++++++++++++-- target/i386/kvm/kvm.c | 3 ++- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f1ce4e3008..99f0d5d851 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1319,7 +1319,8 @@ typedef struct XSavePKRU { #define XSAVE_OPMASK_OFFSET 0x440 #define XSAVE_ZMM_HI256_OFFSET 0x480 #define XSAVE_HI16_ZMM_OFFSET 0x680 -#define XSAVE_PKRU_OFFSET 0xa80 +#define XSAVE_INTEL_PKRU_OFFSET 0xa80 +#define XSAVE_AMD_PKRU_OFFSET 0x980 typedef struct X86XSaveArea { X86LegacyXSaveArea legacy; @@ -1348,6 +1349,16 @@ typedef struct X86XSaveArea { /* PKRU State: */ XSavePKRU pkru_state; } intel; + struct { + /* Ensure that XSavePKRU is properly aligned. */ + uint8_t padding[XSAVE_AMD_PKRU_OFFSET + - sizeof(X86LegacyXSaveArea) + - sizeof(X86XSaveHeader) + - sizeof(XSaveAVX)]; + + /* PKRU State: */ + XSavePKRU pkru_state; + } amd; }; } X86XSaveArea; @@ -1370,7 +1381,9 @@ QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, intel.pkru_state) - != XSAVE_PKRU_OFFSET); + != XSAVE_INTEL_PKRU_OFFSET); +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, amd.pkru_state) + != XSAVE_AMD_PKRU_OFFSET); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); typedef enum TPRAccess { diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 417776a635..9dd7db060d 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2414,7 +2414,8 @@ ASSERT_OFFSET(XSAVE_BNDCSR_OFFSET, intel.bndcsr_state); ASSERT_OFFSET(XSAVE_OPMASK_OFFSET, intel.opmask_state); ASSERT_OFFSET(XSAVE_ZMM_HI256_OFFSET, intel.zmm_hi256_state); ASSERT_OFFSET(XSAVE_HI16_ZMM_OFFSET, intel.hi16_zmm_state); -ASSERT_OFFSET(XSAVE_PKRU_OFFSET, intel.pkru_state); +ASSERT_OFFSET(XSAVE_INTEL_PKRU_OFFSET, intel.pkru_state); +ASSERT_OFFSET(XSAVE_AMD_PKRU_OFFSET, amd.pkru_state); static int kvm_put_xsave(X86CPU *cpu) {