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[142.114.143.47]) by smtp.googlemail.com with ESMTPSA id q22sm778080qtn.25.2021.09.15.13.58.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Sep 2021 13:58:10 -0700 (PDT) From: Shashi Mallela To: peter.maydell@linaro.org Subject: [PATCH] hw/intc: GIC maintenance interrupt not triggered Date: Wed, 15 Sep 2021 16:58:09 -0400 Message-Id: <20210915205809.59068-1-shashi.mallela@linaro.org> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=shashi.mallela@linaro.org; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" During sbsa acs level 3 testing,it is seen that the GIC maintenance interrupts are not triggered and the related test cases failed.On debugging the cause,found that the value of MISR register (from maintenance_interrupt_state()) was being passed to qemu_set_irq() as level.Updated logic to set level to 1 if any of the maintenance interrupt attributes are set. Confirmed that the GIC maintanence interrupts are triggered and sbsa acs test cases passed with this change. Signed-off-by: Shashi Mallela Reviewed-by: Philippe Mathieu-Daudé --- hw/intc/arm_gicv3_cpuif.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 462a35f66e..34691d4fe2 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -418,7 +418,9 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) } if (cs->ich_hcr_el2 & ICH_HCR_EL2_EN) { - maintlevel = maintenance_interrupt_state(cs); + if (maintenance_interrupt_state(cs)) { + maintlevel = 1; + } } trace_gicv3_cpuif_virt_set_irqs(gicv3_redist_affid(cs), fiqlevel,