| Message ID | 20210920080451.408655-4-git@xen0n.name (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | 64-bit LoongArch port of QEMU TCG | expand |
On 9/20/21 1:04 AM, WANG Xuerui wrote: > Signed-off-by: WANG Xuerui <git@xen0n.name> > --- > tcg/loongarch/tcg-target.h | 183 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 183 insertions(+) > create mode 100644 tcg/loongarch/tcg-target.h > > diff --git a/tcg/loongarch/tcg-target.h b/tcg/loongarch/tcg-target.h > new file mode 100644 > index 0000000000..b5e70e01b5 > --- /dev/null > +++ b/tcg/loongarch/tcg-target.h > @@ -0,0 +1,183 @@ > +/* > + * Tiny Code Generator for QEMU > + * > + * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> > + * > + * Based on tcg/riscv/tcg-target.h > + * > + * Copyright (c) 2018 SiFive, Inc You may have copied too much from the riscv port? :-) > +/* > + * Loongson removed the (incomplete) 32-bit support from kernel and toolchain > + * for the initial upstreaming of this architecture, so don't bother and just > + * support the LP64 ABI for now. > + */ > +#if defined(__loongarch64) > +# define TCG_TARGET_REG_BITS 64 > +#else > +# error unsupported LoongArch bitness s/bitness/register size/ > +#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 Hmm. I was about to say this is more copying from riscv, and should be X, but now I see that this is no longer used. You can omit it now; I'll remove the other instances myself. > +/* optional instructions */ > +#define TCG_TARGET_HAS_movcond_i32 0 > +#define TCG_TARGET_HAS_div_i32 1 > +#define TCG_TARGET_HAS_rem_i32 1 > +#define TCG_TARGET_HAS_div2_i32 0 > +#define TCG_TARGET_HAS_rot_i32 1 > +#define TCG_TARGET_HAS_deposit_i32 1 > +#define TCG_TARGET_HAS_extract_i32 1 > +#define TCG_TARGET_HAS_sextract_i32 0 > +#define TCG_TARGET_HAS_extract2_i32 0 > +#define TCG_TARGET_HAS_add2_i32 0 > +#define TCG_TARGET_HAS_sub2_i32 0 > +#define TCG_TARGET_HAS_mulu2_i32 0 > +#define TCG_TARGET_HAS_muls2_i32 0 > +#define TCG_TARGET_HAS_muluh_i32 1 > +#define TCG_TARGET_HAS_mulsh_i32 1 > +#define TCG_TARGET_HAS_ext8s_i32 1 > +#define TCG_TARGET_HAS_ext16s_i32 1 > +#define TCG_TARGET_HAS_ext8u_i32 1 > +#define TCG_TARGET_HAS_ext16u_i32 1 > +#define TCG_TARGET_HAS_bswap16_i32 0 > +#define TCG_TARGET_HAS_bswap32_i32 1 > +#define TCG_TARGET_HAS_not_i32 1 > +#define TCG_TARGET_HAS_neg_i32 1 > +#define TCG_TARGET_HAS_andc_i32 1 > +#define TCG_TARGET_HAS_orc_i32 1 > +#define TCG_TARGET_HAS_eqv_i32 0 > +#define TCG_TARGET_HAS_nand_i32 0 > +#define TCG_TARGET_HAS_nor_i32 1 > +#define TCG_TARGET_HAS_clz_i32 1 > +#define TCG_TARGET_HAS_ctz_i32 1 > +#define TCG_TARGET_HAS_ctpop_i32 0 > +#define TCG_TARGET_HAS_direct_jump 0 > +#define TCG_TARGET_HAS_brcond2 0 > +#define TCG_TARGET_HAS_setcond2 0 > +#define TCG_TARGET_HAS_qemu_st8_i32 0 > + > +#if TCG_TARGET_REG_BITS == 64 You don't need this conditional, since you've asserted it at the top (and unlike riscv, have no plans to add support for riscv32 at some future point).
Hi Richard, On 9/20/21 22:23, Richard Henderson wrote: > On 9/20/21 1:04 AM, WANG Xuerui wrote: >> Signed-off-by: WANG Xuerui <git@xen0n.name> >> --- >> tcg/loongarch/tcg-target.h | 183 +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 183 insertions(+) >> create mode 100644 tcg/loongarch/tcg-target.h >> >> diff --git a/tcg/loongarch/tcg-target.h b/tcg/loongarch/tcg-target.h >> new file mode 100644 >> index 0000000000..b5e70e01b5 >> --- /dev/null >> +++ b/tcg/loongarch/tcg-target.h >> @@ -0,0 +1,183 @@ >> +/* >> + * Tiny Code Generator for QEMU >> + * >> + * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> >> + * >> + * Based on tcg/riscv/tcg-target.h >> + * >> + * Copyright (c) 2018 SiFive, Inc > > You may have copied too much from the riscv port? :-) First of all, thanks for the *extremely* quick review! As for the copying, I admit that I thought the riscv port generally was doing things the recent and preferred way, so most of the logic are only lightly touched. However the LoongArch is substantially similar to riscv too, so much of the traits expressed here would be the same regardless. But in such a case of outstanding similarity, should I just drop my "copyright" line? I'm actually okay with dropping if that's the best thing to do. > >> +/* >> + * Loongson removed the (incomplete) 32-bit support from kernel and >> toolchain >> + * for the initial upstreaming of this architecture, so don't bother >> and just >> + * support the LP64 ABI for now. >> + */ >> +#if defined(__loongarch64) >> +# define TCG_TARGET_REG_BITS 64 >> +#else >> +# error unsupported LoongArch bitness > > s/bitness/register size/ Sure; will fix in v2. > > >> +#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 > > Hmm. I was about to say this is more copying from riscv, and should > be X, but now I see that this is no longer used. You can omit it now; > I'll remove the other instances myself. Thanks for the explanation, I'm only into qemu internals for 2 weeks and that's something I haven't read about yet! I'll try to remove irrelevant parts like this in v2. > >> +/* optional instructions */ >> +#define TCG_TARGET_HAS_movcond_i32 0 >> +#define TCG_TARGET_HAS_div_i32 1 >> +#define TCG_TARGET_HAS_rem_i32 1 >> +#define TCG_TARGET_HAS_div2_i32 0 >> +#define TCG_TARGET_HAS_rot_i32 1 >> +#define TCG_TARGET_HAS_deposit_i32 1 >> +#define TCG_TARGET_HAS_extract_i32 1 >> +#define TCG_TARGET_HAS_sextract_i32 0 >> +#define TCG_TARGET_HAS_extract2_i32 0 >> +#define TCG_TARGET_HAS_add2_i32 0 >> +#define TCG_TARGET_HAS_sub2_i32 0 >> +#define TCG_TARGET_HAS_mulu2_i32 0 >> +#define TCG_TARGET_HAS_muls2_i32 0 >> +#define TCG_TARGET_HAS_muluh_i32 1 >> +#define TCG_TARGET_HAS_mulsh_i32 1 >> +#define TCG_TARGET_HAS_ext8s_i32 1 >> +#define TCG_TARGET_HAS_ext16s_i32 1 >> +#define TCG_TARGET_HAS_ext8u_i32 1 >> +#define TCG_TARGET_HAS_ext16u_i32 1 >> +#define TCG_TARGET_HAS_bswap16_i32 0 >> +#define TCG_TARGET_HAS_bswap32_i32 1 >> +#define TCG_TARGET_HAS_not_i32 1 >> +#define TCG_TARGET_HAS_neg_i32 1 >> +#define TCG_TARGET_HAS_andc_i32 1 >> +#define TCG_TARGET_HAS_orc_i32 1 >> +#define TCG_TARGET_HAS_eqv_i32 0 >> +#define TCG_TARGET_HAS_nand_i32 0 >> +#define TCG_TARGET_HAS_nor_i32 1 >> +#define TCG_TARGET_HAS_clz_i32 1 >> +#define TCG_TARGET_HAS_ctz_i32 1 >> +#define TCG_TARGET_HAS_ctpop_i32 0 >> +#define TCG_TARGET_HAS_direct_jump 0 >> +#define TCG_TARGET_HAS_brcond2 0 >> +#define TCG_TARGET_HAS_setcond2 0 >> +#define TCG_TARGET_HAS_qemu_st8_i32 0 >> + >> +#if TCG_TARGET_REG_BITS == 64 > > You don't need this conditional, since you've asserted it at the top > (and unlike riscv, have no plans to add support for riscv32 at some > future point). OK, will remove all such conditionals in v2 too.
On 9/20/21 9:20 AM, WANG Xuerui wrote: >>> + * Copyright (c) 2018 SiFive, Inc >> >> You may have copied too much from the riscv port? :-) > > First of all, thanks for the *extremely* quick review! > > As for the copying, I admit that I thought the riscv port generally was doing things the > recent and preferred way, so most of the logic are only lightly touched. However the > LoongArch is substantially similar to riscv too, so much of the traits expressed here > would be the same regardless. > > But in such a case of outstanding similarity, should I just drop my "copyright" line? I'm > actually okay with dropping if that's the best thing to do. Yes, your own copyright is the correct thing in this case. r~
diff --git a/tcg/loongarch/tcg-target.h b/tcg/loongarch/tcg-target.h new file mode 100644 index 0000000000..b5e70e01b5 --- /dev/null +++ b/tcg/loongarch/tcg-target.h @@ -0,0 +1,183 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> + * + * Based on tcg/riscv/tcg-target.h + * + * Copyright (c) 2018 SiFive, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef LOONGARCH_TCG_TARGET_H +#define LOONGARCH_TCG_TARGET_H + +/* + * Loongson removed the (incomplete) 32-bit support from kernel and toolchain + * for the initial upstreaming of this architecture, so don't bother and just + * support the LP64 ABI for now. + */ +#if defined(__loongarch64) +# define TCG_TARGET_REG_BITS 64 +#else +# error unsupported LoongArch bitness +#endif + +#define TCG_TARGET_INSN_UNIT_SIZE 4 +#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 +#define TCG_TARGET_NB_REGS 32 +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) + +typedef enum { + TCG_REG_ZERO, + TCG_REG_RA, + TCG_REG_TP, + TCG_REG_SP, + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, + TCG_REG_A4, + TCG_REG_A5, + TCG_REG_A6, + TCG_REG_A7, + TCG_REG_T0, + TCG_REG_T1, + TCG_REG_T2, + TCG_REG_T3, + TCG_REG_T4, + TCG_REG_T5, + TCG_REG_T6, + TCG_REG_T7, + TCG_REG_T8, + TCG_REG_RESERVED, + TCG_REG_S9, + TCG_REG_S0, + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + + /* aliases */ + TCG_AREG0 = TCG_REG_S0, + TCG_GUEST_BASE_REG = TCG_REG_S1, + TCG_REG_TMP0 = TCG_REG_T8, + TCG_REG_TMP1 = TCG_REG_T7, + TCG_REG_TMP2 = TCG_REG_T6, +} TCGReg; + +/* used for function call generation */ +#define TCG_REG_CALL_STACK TCG_REG_SP +#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_CALL_ALIGN_ARGS 1 +#define TCG_TARGET_CALL_STACK_OFFSET 0 + +/* optional instructions */ +#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_div_i32 1 +#define TCG_TARGET_HAS_rem_i32 1 +#define TCG_TARGET_HAS_div2_i32 0 +#define TCG_TARGET_HAS_rot_i32 1 +#define TCG_TARGET_HAS_deposit_i32 1 +#define TCG_TARGET_HAS_extract_i32 1 +#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_extract2_i32 0 +#define TCG_TARGET_HAS_add2_i32 0 +#define TCG_TARGET_HAS_sub2_i32 0 +#define TCG_TARGET_HAS_mulu2_i32 0 +#define TCG_TARGET_HAS_muls2_i32 0 +#define TCG_TARGET_HAS_muluh_i32 1 +#define TCG_TARGET_HAS_mulsh_i32 1 +#define TCG_TARGET_HAS_ext8s_i32 1 +#define TCG_TARGET_HAS_ext16s_i32 1 +#define TCG_TARGET_HAS_ext8u_i32 1 +#define TCG_TARGET_HAS_ext16u_i32 1 +#define TCG_TARGET_HAS_bswap16_i32 0 +#define TCG_TARGET_HAS_bswap32_i32 1 +#define TCG_TARGET_HAS_not_i32 1 +#define TCG_TARGET_HAS_neg_i32 1 +#define TCG_TARGET_HAS_andc_i32 1 +#define TCG_TARGET_HAS_orc_i32 1 +#define TCG_TARGET_HAS_eqv_i32 0 +#define TCG_TARGET_HAS_nand_i32 0 +#define TCG_TARGET_HAS_nor_i32 1 +#define TCG_TARGET_HAS_clz_i32 1 +#define TCG_TARGET_HAS_ctz_i32 1 +#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_direct_jump 0 +#define TCG_TARGET_HAS_brcond2 0 +#define TCG_TARGET_HAS_setcond2 0 +#define TCG_TARGET_HAS_qemu_st8_i32 0 + +#if TCG_TARGET_REG_BITS == 64 +#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_div_i64 1 +#define TCG_TARGET_HAS_rem_i64 1 +#define TCG_TARGET_HAS_div2_i64 0 +#define TCG_TARGET_HAS_rot_i64 1 +#define TCG_TARGET_HAS_deposit_i64 1 +#define TCG_TARGET_HAS_extract_i64 1 +#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extract2_i64 0 +#define TCG_TARGET_HAS_extrl_i64_i32 1 +#define TCG_TARGET_HAS_extrh_i64_i32 1 +#define TCG_TARGET_HAS_ext8s_i64 1 +#define TCG_TARGET_HAS_ext16s_i64 1 +#define TCG_TARGET_HAS_ext32s_i64 1 +#define TCG_TARGET_HAS_ext8u_i64 1 +#define TCG_TARGET_HAS_ext16u_i64 1 +#define TCG_TARGET_HAS_ext32u_i64 1 +#define TCG_TARGET_HAS_bswap16_i64 0 +#define TCG_TARGET_HAS_bswap32_i64 0 +#define TCG_TARGET_HAS_bswap64_i64 1 +#define TCG_TARGET_HAS_not_i64 1 +#define TCG_TARGET_HAS_neg_i64 1 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_orc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 0 +#define TCG_TARGET_HAS_nand_i64 0 +#define TCG_TARGET_HAS_nor_i64 1 +#define TCG_TARGET_HAS_clz_i64 1 +#define TCG_TARGET_HAS_ctz_i64 1 +#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_add2_i64 0 +#define TCG_TARGET_HAS_sub2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muluh_i64 1 +#define TCG_TARGET_HAS_mulsh_i64 1 +#endif + +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); + +#define TCG_TARGET_DEFAULT_MO (0) + +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif + +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 + +#endif /* LOONGARCH_TCG_TARGET_H */
Signed-off-by: WANG Xuerui <git@xen0n.name> --- tcg/loongarch/tcg-target.h | 183 +++++++++++++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) create mode 100644 tcg/loongarch/tcg-target.h