[v8,13/78] target/riscv: rvv-1.0: add fractional LMUL

Message ID	20211015074627.3957162-14-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=d4Ft=PD=nongnu.org=qemu-devel-bounces+qemu-devel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6AC096115C From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL Date: Fri, 15 Oct 2021 15:45:14 +0800 Message-Id: <20211015074627.3957162-14-frank.chang@sifive.com> In-Reply-To: <20211015074627.3957162-1-frank.chang@sifive.com> References: <20211015074627.3957162-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: Frank Chang <frank.chang@sifive.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	support vector extension v1.0 \| expand [v8,00/78] support vector extension v1.0 [v8,01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh [v8,02/78] target/riscv: drop vector 0.7.1 and add 1.0 support [v8,03/78] target/riscv: Use FIELD_EX32() to extract wd field [v8,04/78] target/riscv: rvv-1.0: add mstatus VS field [v8,05/78] target/riscv: rvv-1.0: add sstatus VS field [v8,06/78] target/riscv: rvv-1.0: introduce writable misa.v field [v8,07/78] target/riscv: rvv-1.0: add translation-time vector context status [v8,08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers [v8,09/78] target/riscv: rvv-1.0: add vcsr register [v8,10/78] target/riscv: rvv-1.0: add vlenb register [v8,11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers [v8,12/78] target/riscv: rvv-1.0: remove MLEN calculations [v8,13/78] target/riscv: rvv-1.0: add fractional LMUL [v8,14/78] target/riscv: rvv-1.0: add VMA and VTA [v8,15/78] target/riscv: rvv-1.0: update check functions [v8,16/78] target/riscv: introduce more imm value modes in translator functions [v8,17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function [18/76] target/riscv: rvv-1.0: configure instructions [19/76] target/riscv: rvv-1.0: stride load and store instructions [v8,20/78] target/riscv: rvv-1.0: stride load and store instructions [21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns [v8,22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns [23/76] target/riscv: rvv-1.0: amo operations [v8,24/78] target/riscv: rvv-1.0: load/store whole register instructions [v8,25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns [v8,26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation [v8,27/78] target/riscv: rvv-1.0: floating-point square-root instruction [v8,28/78] target/riscv: rvv-1.0: floating-point classify instructions [29/76] target/riscv: rvv-1.0: mask population count instruction [v8,30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction [v8,31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions [v8,32/78] target/riscv: rvv-1.0: iota instruction [v8,33/78] target/riscv: rvv-1.0: element index instruction [v8,34/78] target/riscv: rvv-1.0: allow load element with sign-extended [v8,35/78] target/riscv: rvv-1.0: register gather instructions [v8,36/78] target/riscv: rvv-1.0: integer scalar move instructions [v8,37/78] target/riscv: rvv-1.0: floating-point move instruction [v8,38/78] target/riscv: rvv-1.0: floating-point scalar move instructions [v8,39/78] target/riscv: rvv-1.0: whole register move instructions [v8,40/78] target/riscv: rvv-1.0: integer extension instructions [v8,41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions [v8,42/78] target/riscv: rvv-1.0: single-width bit shift instructions [v8,43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow [v8,44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions [v8,45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions [v8,46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions [v8,47/78] target/riscv: rvv-1.0: integer comparison instructions [v8,48/78] target/riscv: rvv-1.0: floating-point compare instructions [v8,49/78] target/riscv: rvv-1.0: mask-register logical instructions [v8,50/78] target/riscv: rvv-1.0: slide instructions [v8,51/78] target/riscv: rvv-1.0: floating-point slide instructions [v8,52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions [v8,53/78] target/riscv: rvv-1.0: single-width floating-point reduction [v8,54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions [v8,55/78] target/riscv: rvv-1.0: single-width scaling shift instructions [v8,56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add [v8,57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf [v8,58/78] target/riscv: rvv-1.0: remove integer extract instruction [v8,59/78] target/riscv: rvv-1.0: floating-point min/max instructions [v8,60/78] target/riscv: introduce floating-point rounding mode enum [v8,61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions [v8,62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert [v8,63/78] target/riscv: add "set round to odd" rounding mode helper function [v8,64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert [v8,65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits [v8,66/78] target/riscv: rvv-1.0: implement vstart CSR [v8,67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid [v8,68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs [v8,69/78] target/riscv: gdb: support vector registers for rv64 & rv32 [v8,70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction [v8,71/78] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction [v8,72/78] target/riscv: set mstatus.SD bit when writing fp CSRs [v8,73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 [v8,74/78] target/riscv: rvv-1.0: add vsetivli instruction [v8,75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() [v8,76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns [v8,77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm [v8,78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment

Message ID

20211015074627.3957162-14-frank.chang@sifive.com (mailing list archive)

State

New, archived

Headers

DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6AC096115C
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL
Date: Fri, 15 Oct 2021 15:45:14 +0800
Message-Id: <20211015074627.3957162-14-frank.chang@sifive.com>
In-Reply-To: <20211015074627.3957162-1-frank.chang@sifive.com>
References: <20211015074627.3957162-1-frank.chang@sifive.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Received-SPF: pass client-ip=2607:f8b0:4864:20::62f;
 envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62f.google.com
X-Spam_score_int: -20
X-Spam_score: -2.1
X-Spam_bar: --
X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,
 DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,
 RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,
 SPF_PASS=-0.001 autolearn=ham autolearn_force=no
X-Spam_action: no action
X-BeenThere: qemu-devel@nongnu.org
X-Mailman-Version: 2.1.23
Precedence: list
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
 <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
 <mailto:qemu-devel-request@nongnu.org?subject=subscribe>
Cc: Frank Chang <frank.chang@sifive.com>,
 Alistair Francis <alistair.francis@wdc.com>,
 Bin Meng <bin.meng@windriver.com>,
 Richard Henderson <richard.henderson@linaro.org>,
 Palmer Dabbelt <palmer@dabbelt.com>
Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org
Sender: "Qemu-devel"
 <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>

Series

support vector extension v1.0 | expand

Commit Message

Frank Chang Oct. 15, 2021, 7:45 a.m. UTC

From: Frank Chang <frank.chang@sifive.com>

Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.

Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
and MSTATUS_FS (0x6000) bits.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h           | 22 ++++++++++++----------
 target/riscv/translate.c     | 16 ++++++++++++++--
 target/riscv/vector_helper.c | 16 ++++++++++++++--
 3 files changed, 40 insertions(+), 14 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fb41c1cea7c..1bd9b4123da 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -103,10 +103,10 @@  typedef struct CPURISCVState CPURISCVState;
 
 #define RV_VLEN_MAX 256
 
-FIELD(VTYPE, VLMUL, 0, 2)
-FIELD(VTYPE, VSEW, 2, 3)
-FIELD(VTYPE, VEDIV, 5, 2)
-FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
+FIELD(VTYPE, VLMUL, 0, 3)
+FIELD(VTYPE, VSEW, 3, 3)
+FIELD(VTYPE, VEDIV, 8, 2)
+FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
 
 struct CPURISCVState {
@@ -391,14 +391,16 @@  typedef RISCVCPU ArchCPU;
 #include "exec/cpu-all.h"
 
 FIELD(TB_FLAGS, MEM_IDX, 0, 3)
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
-FIELD(TB_FLAGS, LMUL, 4, 2)
+FIELD(TB_FLAGS, LMUL, 3, 3)
 FIELD(TB_FLAGS, SEW, 6, 3)
-FIELD(TB_FLAGS, VILL, 9, 1)
+/* Skip MSTATUS_VS (0x600) bits */
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
+FIELD(TB_FLAGS, VILL, 12, 1)
+/* Skip MSTATUS_FS (0x6000) bits */
 /* Is a Hypervisor instruction load/store allowed? */
-FIELD(TB_FLAGS, HLSX, 10, 1)
-FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
-FIELD(TB_FLAGS, MSTATUS_HS_VS, 13, 2)
+FIELD(TB_FLAGS, HLSX, 15, 1)
+FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
+FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
 
 bool riscv_cpu_is_32bit(CPURISCVState *env);
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 174ef0564e6..6a3f105d431 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -76,7 +76,19 @@  typedef struct DisasContext {
     bool hlsx;
     /* vector extension */
     bool vill;
-    uint8_t lmul;
+    /*
+     * Encode LMUL to lmul as follows:
+     *     LMUL    vlmul    lmul
+     *      1       000       0
+     *      2       001       1
+     *      4       010       2
+     *      8       011       3
+     *      -       100       -
+     *     1/8      101      -3
+     *     1/4      110      -2
+     *     1/2      111      -1
+     */
+    int8_t lmul;
     uint8_t sew;
     uint16_t vlen;
     bool vl_eq_vlmax;
@@ -606,7 +618,7 @@  static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
     ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
-    ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
+    ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
     ctx->cs = cs;
     ctx->w = false;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ac6c7298bc0..866bfb35714 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -86,9 +86,21 @@  static inline uint32_t vext_vm(uint32_t desc)
     return FIELD_EX32(simd_data(desc), VDATA, VM);
 }
 
-static inline uint32_t vext_lmul(uint32_t desc)
+/*
+ * Encode LMUL to lmul as following:
+ *     LMUL    vlmul    lmul
+ *      1       000       0
+ *      2       001       1
+ *      4       010       2
+ *      8       011       3
+ *      -       100       -
+ *     1/8      101      -3
+ *     1/4      110      -2
+ *     1/2      111      -1
+ */
+static inline int32_t vext_lmul(uint32_t desc)
 {
-    return FIELD_EX32(simd_data(desc), VDATA, LMUL);
+    return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
 }
 
 static uint32_t vext_wd(uint32_t desc)

[v8,13/78] target/riscv: rvv-1.0: add fractional LMUL

Commit Message

Patch