diff mbox series

[v5,8/8] target/riscv: zfh: add Zfhmin cpu property

Message ID 20211021162956.2772656-9-frank.chang@sifive.com (mailing list archive)
State New, archived
Headers show
Series [v5,1/8] target/riscv: zfh: half-precision load and store | expand

Commit Message

Frank Chang Oct. 21, 2021, 4:29 p.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1b3a7784b06..e6e3ef183ae 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -618,6 +618,7 @@  static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
+    DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),