From patchwork Fri Oct 29 08:58:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 12592349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D142FC433F5 for ; Fri, 29 Oct 2021 09:52:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5A28460EFF for ; Fri, 29 Oct 2021 09:52:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5A28460EFF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:59178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgOYg-0000Qq-AI for qemu-devel@archiver.kernel.org; Fri, 29 Oct 2021 05:52:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35266) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgNlw-0006Hc-2p for qemu-devel@nongnu.org; Fri, 29 Oct 2021 05:02:00 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:34432) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgNlu-00067c-Bo for qemu-devel@nongnu.org; Fri, 29 Oct 2021 05:01:59 -0400 Received: by mail-pj1-x1031.google.com with SMTP id q2-20020a17090a2e0200b001a0fd4efd49so6995996pjd.1 for ; Fri, 29 Oct 2021 02:01:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/OK8ndHXebSuebbcYtIDS8BUmBXZpM2FFEmiamjCuDY=; b=BK1ZO9/ZaqLSoIx1sH7OQawVlOMYAI5fNMVJhZmBGR1xMRO81IJfixEAQga6k847D6 mpmZVrgOz4GYSM+AeHCM/qr/+fVFjPC6Lngm0Bc/Qf4auHIYLST+68mo6DyHN/XeGqrf o/67GHS6u1wtet3QNBcZM6O5K3kEiH2wCphvPubO8FVxVPwOZGNF0+qOgpVmXTNj63NQ U5yT8sQ14H0ygSDiTt7+2jxNqO1BDNh4/fR60KC87Ehwm0cPN3/13eH2nZvPuqXGUzee h3Ajy46Sbx/jdcnirGjCvZ7EbNwt6PxqD1tAdzpSkABOmbrOiHb2aLllnRXDKoD2kP71 Au3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/OK8ndHXebSuebbcYtIDS8BUmBXZpM2FFEmiamjCuDY=; b=ZuhzpMbSOWYEuc9t8kgo0KGq6iDdt915AzUouHGz5PC9vzKzuzHDhvOhKsl8Ey8bIM hhk5cOehGeGmoAcktFP4c9nh8t1D8vcUlr2xAzYCHOagZdyqsCFzfCXimgsglApxeYjD /fRq8vCZOA4M8KaGhPzeFKM7QlsGrzJ7fTr4ltzaY4ufCKulM0w0p6yHBvqsvHkkhXTG dBsUnR/LZYQUsiqEebeXoDJDth8EOGFwqdLMm32w+UIg7JrEfeDLQNK4l0SzlCyUY6Nk bPBAKD2Bjqtd5I7hAOmv6WRpZkJp3Bq4K2Zxwz5ST2PnXn18Fi+2KGKAAi2PV+vnWp/r fnww== X-Gm-Message-State: AOAM530i35lfVNL+Cf4MQUjjud/VJRmpVazmOuko1JetI0O8czaNXfro B4IziHylrAV4fIdYEdxM55U6rDgMQPhSBXNx X-Google-Smtp-Source: ABdhPJwXIq5ErabwkZ47O0DHTqKrrcVyUv6Q2PkS5iMyuW0xPC2mcC/RNeIZCjcNis9zDsRt/kGYiA== X-Received: by 2002:a17:90b:4a07:: with SMTP id kk7mr10204223pjb.37.1635498116975; Fri, 29 Oct 2021 02:01:56 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:46b:ce55:983b:6962:38ac:e1b9]) by smtp.gmail.com with ESMTPSA id t13sm5081477pgn.94.2021.10.29.02.01.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Oct 2021 02:01:56 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v9 38/76] target/riscv: rvv-1.0: floating-point scalar move instructions Date: Fri, 29 Oct 2021 16:58:43 +0800 Message-Id: <20211029085922.255197-39-frank.chang@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029085922.255197-1-frank.chang@sifive.com> References: <20211029085922.255197-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang NaN-boxed the scalar floating-point register based on RVV 1.0's rules. Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/insn32.decode | 4 +-- target/riscv/insn_trans/trans_rvv.c.inc | 38 ++++++++++++------------- target/riscv/internals.h | 5 ---- 3 files changed, 21 insertions(+), 26 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e33ec82fdf8..ab5fdbf9be8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -637,8 +637,8 @@ vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2 vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r -vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd -vfmv_s_f 001101 1 00000 ..... 101 ..... 1010111 @r2 +vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd +vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2 vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 2c8002af543..89f88a0ea70 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3047,14 +3047,19 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) /* Floating-Point Scalar Move Instructions */ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) { - if (!s->vill && has_ext(s, RVF) && - (s->mstatus_fs != 0) && (s->sew != 0)) { - unsigned int len = 8 << s->sew; + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s)) { + unsigned int ofs = (8 << s->sew); + unsigned int len = 64 - ofs; + TCGv_i64 t_nan; vec_element_loadi(s, cpu_fpr[a->rd], a->rs2, 0, false); - if (len < 64) { - tcg_gen_ori_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], - MAKE_64BIT_MASK(len, 64 - len)); + /* NaN-box f[rd] as necessary for SEW */ + if (len) { + t_nan = tcg_constant_i64(UINT64_MAX); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], + t_nan, ofs, len); } mark_fs_dirty(s); @@ -3066,25 +3071,20 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) /* vfmv.s.f vd, rs1 # vd[0] = rs1 (vs2=0) */ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) { - if (!s->vill && has_ext(s, RVF) && (s->sew != 0)) { - TCGv_i64 t1; + if (require_rvv(s) && + require_rvf(s) && + vext_check_isa_ill(s)) { /* The instructions ignore LMUL and vector register group. */ - uint32_t vlmax = s->vlen >> 3; + TCGv_i64 t1; + TCGLabel *over = gen_new_label(); /* if vl == 0, skip vector register write back */ - TCGLabel *over = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); - /* zeroed all elements */ - tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), vlmax, vlmax, 0); - - /* NaN-box f[rs1] as necessary for SEW */ + /* NaN-box f[rs1] */ t1 = tcg_temp_new_i64(); - if (s->sew == MO_64 && !has_ext(s, RVD)) { - tcg_gen_ori_i64(t1, cpu_fpr[a->rs1], MAKE_64BIT_MASK(32, 32)); - } else { - tcg_gen_mov_i64(t1, cpu_fpr[a->rs1]); - } + do_nanbox(s, t1, cpu_fpr[a->rs1]); + vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); mark_vs_dirty(s); diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 81f5dfa477a..ac062dc0b4e 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -32,11 +32,6 @@ target_ulong fclass_h(uint64_t frs1); target_ulong fclass_s(uint64_t frs1); target_ulong fclass_d(uint64_t frs1); -#define SEW8 0 -#define SEW16 1 -#define SEW32 2 -#define SEW64 3 - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_riscv_cpu; #endif