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Fri, 29 Oct 2021 02:03:24 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v9 60/76] target/riscv: introduce floating-point rounding mode enum Date: Fri, 29 Oct 2021 16:59:05 +0800 Message-Id: <20211029085922.255197-61-frank.chang@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029085922.255197-1-frank.chang@sifive.com> References: <20211029085922.255197-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/fpu_helper.c | 12 ++++++------ target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++--------- target/riscv/internals.h | 9 +++++++++ 3 files changed, 24 insertions(+), 15 deletions(-) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 388e23ca670..dec39d4a9ed 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -55,23 +55,23 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) { int softrm; - if (rm == 7) { + if (rm == RISCV_FRM_DYN) { rm = env->frm; } switch (rm) { - case 0: + case RISCV_FRM_RNE: softrm = float_round_nearest_even; break; - case 1: + case RISCV_FRM_RTZ: softrm = float_round_to_zero; break; - case 2: + case RISCV_FRM_RDN: softrm = float_round_down; break; - case 3: + case RISCV_FRM_RUP: softrm = float_round_up; break; - case 4: + case RISCV_FRM_RMM: softrm = float_round_ties_away; break; default: diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 1ce5a10b6a8..047be5d5c47 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2088,7 +2088,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_d, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2167,7 +2167,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_w, \ gen_helper_##NAME##_d, \ }; \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2199,7 +2199,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2236,7 +2236,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ static gen_helper_opfvf *const fns[2] = { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2266,7 +2266,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2303,7 +2303,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ static gen_helper_opfvf *const fns[2] = { \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ }; \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ @@ -2380,7 +2380,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_helper_##NAME##_d, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2526,7 +2526,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ @@ -2574,7 +2574,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_helper_##NAME##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, 7); \ + gen_set_rm(s, RISCV_FRM_DYN); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ \ data = FIELD_DP32(data, VDATA, VM, a->vm); \ diff --git a/target/riscv/internals.h b/target/riscv/internals.h index ac062dc0b4e..db105d4d640 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -36,6 +36,15 @@ target_ulong fclass_d(uint64_t frs1); extern const VMStateDescription vmstate_riscv_cpu; #endif +enum { + RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */ + RISCV_FRM_RTZ = 1, /* Round towards Zero */ + RISCV_FRM_RDN = 2, /* Round Down */ + RISCV_FRM_RUP = 3, /* Round Up */ + RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */ + RISCV_FRM_DYN = 7, /* Dynamic rounding mode */ +}; + static inline uint64_t nanbox_s(float32 f) { return f | MAKE_64BIT_MASK(32, 32);