[v9,07/76] target/riscv: rvv-1.0: add translation-time vector context status

Message ID	20211029085922.255197-8-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=w/R+=PR=nongnu.org=qemu-devel-bounces+qemu-devel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org BAE2860F9C From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v9 07/76] target/riscv: rvv-1.0: add translation-time vector context status Date: Fri, 29 Oct 2021 16:58:12 +0800 Message-Id: <20211029085922.255197-8-frank.chang@sifive.com> In-Reply-To: <20211029085922.255197-1-frank.chang@sifive.com> References: <20211029085922.255197-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	support vector extension v1.0 \| expand [v9,00/76] support vector extension v1.0 [v9,01/76] target/riscv: drop vector 0.7.1 and add 1.0 support [v9,02/76] target/riscv: Use FIELD_EX32() to extract wd field [v9,03/76] target/riscv: rvv-1.0: add mstatus VS field [v9,04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty [v9,05/76] target/riscv: rvv-1.0: add sstatus VS field [v9,06/76] target/riscv: rvv-1.0: introduce writable misa.v field [v9,07/76] target/riscv: rvv-1.0: add translation-time vector context status [v9,08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers [v9,09/76] target/riscv: rvv-1.0: add vcsr register [v9,10/76] target/riscv: rvv-1.0: add vlenb register [v9,11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers [v9,12/76] target/riscv: rvv-1.0: remove MLEN calculations [v9,13/76] target/riscv: rvv-1.0: add fractional LMUL [v9,14/76] target/riscv: rvv-1.0: add VMA and VTA [v9,15/76] target/riscv: rvv-1.0: update check functions [v9,16/76] target/riscv: introduce more imm value modes in translator functions [v9,17/76] target/riscv: rvv:1.0: add translation-time nan-box helper function [v9,18/76] target/riscv: rvv-1.0: remove amo operations instructions [v9,19/76] target/riscv: rvv-1.0: configure instructions [v9,20/76] target/riscv: rvv-1.0: stride load and store instructions [v9,21/76] target/riscv: rvv-1.0: index load and store instructions [v9,22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns [v9,23/76] target/riscv: rvv-1.0: fault-only-first unit stride load [v9,24/76] target/riscv: rvv-1.0: load/store whole register instructions [v9,25/76] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns [v9,26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation [v9,27/76] target/riscv: rvv-1.0: floating-point square-root instruction [v9,28/76] target/riscv: rvv-1.0: floating-point classify instructions [v9,29/76] target/riscv: rvv-1.0: count population in mask instruction [v9,30/76] target/riscv: rvv-1.0: find-first-set mask bit instruction [v9,31/76] target/riscv: rvv-1.0: set-X-first mask bit instructions [v9,32/76] target/riscv: rvv-1.0: iota instruction [v9,33/76] target/riscv: rvv-1.0: element index instruction [v9,34/76] target/riscv: rvv-1.0: allow load element with sign-extended [v9,35/76] target/riscv: rvv-1.0: register gather instructions [v9,36/76] target/riscv: rvv-1.0: integer scalar move instructions [v9,37/76] target/riscv: rvv-1.0: floating-point move instruction [v9,38/76] target/riscv: rvv-1.0: floating-point scalar move instructions [v9,39/76] target/riscv: rvv-1.0: whole register move instructions [v9,40/76] target/riscv: rvv-1.0: integer extension instructions [v9,41/76] target/riscv: rvv-1.0: single-width averaging add and subtract instructions [v9,42/76] target/riscv: rvv-1.0: single-width bit shift instructions [v9,43/76] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow [v9,44/76] target/riscv: rvv-1.0: narrowing integer right shift instructions [v9,45/76] target/riscv: rvv-1.0: widening integer multiply-add instructions [v9,46/76] target/riscv: rvv-1.0: single-width saturating add and subtract instructions [v9,47/76] target/riscv: rvv-1.0: integer comparison instructions [v9,48/76] target/riscv: rvv-1.0: floating-point compare instructions [v9,49/76] target/riscv: rvv-1.0: mask-register logical instructions [v9,50/76] target/riscv: rvv-1.0: slide instructions [v9,51/76] target/riscv: rvv-1.0: floating-point slide instructions [v9,52/76] target/riscv: rvv-1.0: narrowing fixed-point clip instructions [v9,53/76] target/riscv: rvv-1.0: single-width floating-point reduction [v9,54/76] target/riscv: rvv-1.0: widening floating-point reduction instructions [v9,55/76] target/riscv: rvv-1.0: single-width scaling shift instructions [v9,56/76] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add [v9,57/76] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf [v9,58/76] target/riscv: rvv-1.0: remove integer extract instruction [v9,59/76] target/riscv: rvv-1.0: floating-point min/max instructions [v9,60/76] target/riscv: introduce floating-point rounding mode enum [v9,61/76] target/riscv: rvv-1.0: floating-point/integer type-convert instructions [v9,62/76] target/riscv: rvv-1.0: widening floating-point/integer type-convert [v9,63/76] target/riscv: add "set round to odd" rounding mode helper function [v9,64/76] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert [v9,65/76] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits [v9,66/76] target/riscv: rvv-1.0: implement vstart CSR [v9,67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid [v9,68/76] target/riscv: gdb: support vector registers for rv64 & rv32 [v9,69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction [v9,70/76] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction [v9,71/76] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 [v9,72/76] target/riscv: rvv-1.0: add vsetivli instruction [v9,73/76] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() [v9,74/76] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns [v9,75/76] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm [v9,76/76] target/riscv: rvv-1.0: update opivv_vadc_check() comment

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 48b8f612109..eee2a2b19ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -410,10 +410,11 @@ FIELD(TB_FLAGS, VILL, 9, 1) /* Is a Hypervisor instruction load/store allowed? */ FIELD(TB_FLAGS, HLSX, 10, 1) FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2) +FIELD(TB_FLAGS, MSTATUS_HS_VS, 13, 2) /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ -FIELD(TB_FLAGS, XL, 13, 2) +FIELD(TB_FLAGS, XL, 15, 2) /* If PointerMasking should be applied */ -FIELD(TB_FLAGS, PM_ENABLED, 15, 1) +FIELD(TB_FLAGS, PM_ENABLED, 17, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5789c2e9690..7149657edf9 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -111,6 +111,9 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS, get_field(env->mstatus_hs, MSTATUS_FS)); + + flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS, + get_field(env->mstatus_hs, MSTATUS_VS)); } if (riscv_has_ext(env, RVJ)) { int priv = flags & TB_FLAGS_PRIV_MMU_MASK; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 17ee3babefd..bc1d4a5f235 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -39,6 +39,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a) } gen_helper_vsetvl(dst, cpu_env, s1, s2); gen_set_gpr(ctx, a->rd, dst); + mark_vs_dirty(ctx); tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn); tcg_gen_lookup_and_goto_ptr(); @@ -66,6 +67,7 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a) } gen_helper_vsetvl(dst, cpu_env, s1, s2); gen_set_gpr(ctx, a->rd, dst); + mark_vs_dirty(ctx); gen_goto_tb(ctx, 0, ctx->pc_succ_insn); ctx->base.is_jmp = DISAS_NORETURN; @@ -154,7 +156,8 @@ typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv, TCGv_env, TCGv_i32); static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, - gen_helper_ldst_us *fn, DisasContext *s) + gen_helper_ldst_us *fn, DisasContext *s, + bool is_store) { TCGv_ptr dest, mask; TCGv base; @@ -183,6 +186,11 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); + + if (!is_store) { + mark_vs_dirty(s); + } + gen_set_label(over); return true; } @@ -233,7 +241,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); } static bool ld_us_check(DisasContext *s, arg_r2nfvm* a) @@ -286,7 +294,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s); + return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); } static bool st_us_check(DisasContext *s, arg_r2nfvm* a) @@ -309,7 +317,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv, static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, uint32_t data, gen_helper_ldst_stride *fn, - DisasContext *s) + DisasContext *s, bool is_store) { TCGv_ptr dest, mask; TCGv base, stride; @@ -331,6 +339,11 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); + + if (!is_store) { + mark_vs_dirty(s); + } + gen_set_label(over); return true; } @@ -365,7 +378,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } static bool ld_stride_check(DisasContext *s, arg_rnfvm* a) @@ -409,7 +422,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) return false; } - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } static bool st_stride_check(DisasContext *s, arg_rnfvm* a) @@ -432,7 +445,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv, static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t data, gen_helper_ldst_index *fn, - DisasContext *s) + DisasContext *s, bool is_store) { TCGv_ptr dest, mask, index; TCGv base; @@ -456,6 +469,11 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(index); + + if (!is_store) { + mark_vs_dirty(s); + } + gen_set_label(over); return true; } @@ -490,7 +508,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); } /* @@ -542,7 +560,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); } static bool st_index_check(DisasContext *s, arg_rnfvm* a) @@ -583,6 +601,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -659,6 +678,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(index); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -810,6 +830,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn, vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fn); } + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -861,6 +882,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -892,6 +914,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn, src1, MAXSZ(s), MAXSZ(s)); tcg_temp_free_i64(src1); + mark_vs_dirty(s); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1003,6 +1026,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1026,10 +1050,10 @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn, gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), sextract64(a->rs1, 0, 5), MAXSZ(s), MAXSZ(s)); } - } else { - return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); + mark_vs_dirty(s); + return true; } - return true; + return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, zx); } /* OPIVI with GVEC IR */ @@ -1089,6 +1113,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a, vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1176,6 +1201,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a, vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fn); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1255,6 +1281,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1383,6 +1410,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn, src1, MAXSZ(s), MAXSZ(s)); tcg_temp_free_i32(src1); + mark_vs_dirty(s); return true; } return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s); @@ -1442,6 +1470,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1626,6 +1655,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) fns[s->sew]); gen_set_label(over); } + mark_vs_dirty(s); return true; } return false; @@ -1665,6 +1695,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) tcg_temp_free_i64(s1_i64); } + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1680,6 +1711,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), simm); + mark_vs_dirty(s); } else { TCGv_i32 desc; TCGv_i64 s1; @@ -1699,6 +1731,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) fns[s->sew](dest, s1, cpu_env, desc); tcg_temp_free_ptr(dest); + mark_vs_dirty(s); gen_set_label(over); } return true; @@ -1804,6 +1837,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1838,6 +1872,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, tcg_temp_free_ptr(dest); tcg_temp_free_ptr(mask); tcg_temp_free_ptr(src2); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -1916,6 +1951,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -1991,6 +2027,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2106,6 +2143,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2178,6 +2216,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) if (s->vl_eq_vlmax) { tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), cpu_fpr[a->rs1]); + mark_vs_dirty(s); } else { TCGv_ptr dest; TCGv_i32 desc; @@ -2196,6 +2235,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc); tcg_temp_free_ptr(dest); + mark_vs_dirty(s); gen_set_label(over); } return true; @@ -2246,6 +2286,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2295,6 +2336,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, \ fns[s->sew - 1]); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2357,6 +2399,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ s->vlen / 8, s->vlen / 8, data, fn); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2451,6 +2494,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ cpu_env, s->vlen / 8, s->vlen / 8, \ data, fn); \ + mark_vs_dirty(s); \ gen_set_label(over); \ return true; \ } \ @@ -2482,6 +2526,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2508,6 +2553,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a) tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), cpu_env, s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2681,6 +2727,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]); vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); + mark_vs_dirty(s); done: gen_set_label(over); return true; @@ -2731,6 +2778,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) } vec_element_storei(s, a->rd, 0, t1); tcg_temp_free_i64(t1); + mark_vs_dirty(s); gen_set_label(over); return true; } @@ -2797,6 +2845,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a) tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), dest); tcg_temp_free_i64(dest); + mark_vs_dirty(s); } else { static gen_helper_opivx * const fns[4] = { gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, @@ -2823,6 +2872,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a) endian_ofs(s, a->rs2, a->rs1), MAXSZ(s), MAXSZ(s)); } + mark_vs_dirty(s); } else { static gen_helper_opivx * const fns[4] = { gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h, @@ -2860,6 +2910,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a) vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->vlen / 8, s->vlen / 8, data, fns[s->sew]); + mark_vs_dirty(s); gen_set_label(over); return true; } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d445954dc76..8051090d2f4 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -62,7 +62,9 @@ typedef struct DisasContext { uint32_t misa_ext; uint32_t opcode; uint32_t mstatus_fs; + uint32_t mstatus_vs; uint32_t mstatus_hs_fs; + uint32_t mstatus_hs_vs; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -348,6 +350,42 @@ static void mark_fs_dirty(DisasContext *ctx) static inline void mark_fs_dirty(DisasContext *ctx) { } #endif +#ifndef CONFIG_USER_ONLY +/* The states of mstatus_vs are: + * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty + * We will have already diagnosed disabled state, + * and need to turn initial/clean into dirty. + */ +static void mark_vs_dirty(DisasContext *ctx) +{ + TCGv tmp; + + if (ctx->mstatus_vs != MSTATUS_VS) { + /* Remember the state change for the rest of the TB. */ + ctx->mstatus_vs = MSTATUS_VS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_temp_free(tmp); + } + + if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { + /* Remember the stage change for the rest of the TB. */ + ctx->mstatus_hs_vs = MSTATUS_VS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_temp_free(tmp); + } +} +#else +static inline void mark_vs_dirty(DisasContext *ctx) { } +#endif + static void gen_set_rm(DisasContext *ctx, int rm) { if (ctx->frm == rm) { @@ -631,6 +669,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->pc_succ_insn = ctx->base.pc_first; ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; + ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; ctx->priv_ver = env->priv_ver; #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { @@ -648,6 +687,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; ctx->vlen = cpu->cfg.vlen; ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); + ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);

[v9,07/76] target/riscv: rvv-1.0: add translation-time vector context status

Commit Message

Patch