From patchwork Tue Nov 9 05:51:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 12609765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E2DDC433F5 for ; Tue, 9 Nov 2021 06:27:52 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A0CF611BF for ; Tue, 9 Nov 2021 06:27:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9A0CF611BF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:35830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkKbm-0007vb-KW for qemu-devel@archiver.kernel.org; Tue, 09 Nov 2021 01:27:50 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50226) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkK41-0004lF-6p; Tue, 09 Nov 2021 00:52:57 -0500 Received: from gandalf.ozlabs.org ([150.107.74.76]:41939) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkK3v-0006ph-Mp; Tue, 09 Nov 2021 00:52:56 -0500 Received: by gandalf.ozlabs.org (Postfix, from userid 1007) id 4HpHDp39pYz4xf5; Tue, 9 Nov 2021 16:52:10 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gibson.dropbear.id.au; s=201602; t=1636437130; bh=znVbTx17nZEXrWAYXF466ivna1Y/xkMNQ6gAnyXIBz8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Di5Kzae++36PnbfQaNCkgZzPQiBH7AsMVNzF3YrK/ZeDBxYbLsTXiQbPSbQecY7FC fSaIWA+ovu5bRiECQOdrqSDacUYvoxT7wrangYcSZNPDxly8QK43FKBHvNLxIAQebT 0UjDTo5KqE0e9KDslEorJ3PY47Ku9WmPujMMtea0= From: David Gibson To: peter.maydell@linaro.org, clg@kaod.org, danielhb413@gmail.com, groug@kaod.org Subject: [PULL 28/54] target/ppc: Move vcfuged to vmx-impl.c.inc Date: Tue, 9 Nov 2021 16:51:38 +1100 Message-Id: <20211109055204.230765-29-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211109055204.230765-1-david@gibson.dropbear.id.au> References: <20211109055204.230765-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=150.107.74.76; envelope-from=dgibson@gandalf.ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matheus Ferst , Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Matheus Ferst There's no reason to keep vector-impl.c.inc separate from vmx-impl.c.inc. Additionally, let GVec handle the multiple calls to helper_cfuged for us. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst Message-Id: <20211104123719.323713-2-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson --- target/ppc/helper.h | 2 +- target/ppc/int_helper.c | 2 +- target/ppc/translate.c | 1 - target/ppc/translate/fixedpoint-impl.c.inc | 2 +- target/ppc/translate/vector-impl.c.inc | 48 ---------------------- target/ppc/translate/vmx-impl.c.inc | 16 ++++++++ 6 files changed, 19 insertions(+), 52 deletions(-) delete mode 100644 target/ppc/translate/vector-impl.c.inc diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 72e66c5fe8..401575b935 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -46,7 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32) DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_3(sraw, tl, env, tl, tl) -DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(CFUGED, TCG_CALL_NO_RWG_SE, i64, i64, i64) #if defined(TARGET_PPC64) DEF_HELPER_FLAGS_2(PDEPD, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(PEXTD, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 913d76be6e..f03c864e48 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -324,7 +324,7 @@ target_ulong helper_popcntb(target_ulong val) } #endif -uint64_t helper_cfuged(uint64_t src, uint64_t mask) +uint64_t helper_CFUGED(uint64_t src, uint64_t mask) { /* * Instead of processing the mask bit-by-bit from the most significant to diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 659859ff5f..fc9d35a7a8 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7407,7 +7407,6 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) #include "translate/vmx-impl.c.inc" #include "translate/vsx-impl.c.inc" -#include "translate/vector-impl.c.inc" #include "translate/dfp-impl.c.inc" diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 220b099fcd..fa519c2d3e 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -407,7 +407,7 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a) REQUIRE_64BIT(ctx); REQUIRE_INSNS_FLAGS2(ctx, ISA310); #if defined(TARGET_PPC64) - gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]); + gen_helper_CFUGED(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]); #else qemu_build_not_reached(); #endif diff --git a/target/ppc/translate/vector-impl.c.inc b/target/ppc/translate/vector-impl.c.inc deleted file mode 100644 index 197e903337..0000000000 --- a/target/ppc/translate/vector-impl.c.inc +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Power ISA decode for Vector Facility instructions - * - * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a) -{ - TCGv_i64 tgt, src, mask; - - REQUIRE_INSNS_FLAGS2(ctx, ISA310); - REQUIRE_VECTOR(ctx); - - tgt = tcg_temp_new_i64(); - src = tcg_temp_new_i64(); - mask = tcg_temp_new_i64(); - - /* centrifuge lower double word */ - get_cpu_vsrl(src, a->vra + 32); - get_cpu_vsrl(mask, a->vrb + 32); - gen_helper_cfuged(tgt, src, mask); - set_cpu_vsrl(a->vrt + 32, tgt); - - /* centrifuge higher double word */ - get_cpu_vsrh(src, a->vra + 32); - get_cpu_vsrh(mask, a->vrb + 32); - gen_helper_cfuged(tgt, src, mask); - set_cpu_vsrh(a->vrt + 32, tgt); - - tcg_temp_free_i64(tgt); - tcg_temp_free_i64(src); - tcg_temp_free_i64(mask); - - return true; -} diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 92b9527aff..e36c66589c 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1559,6 +1559,22 @@ GEN_VXFORM3(vpermxor, 22, 0xFF) GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, vpermxor, PPC_NONE, PPC2_ALTIVEC_207) +static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a) +{ + static const GVecGen3 g = { + .fni8 = gen_helper_CFUGED, + .vece = MO_64, + }; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra), + avr_full_offset(a->vrb), 16, 16, &g); + + return true; +} + #undef GEN_VR_LDX #undef GEN_VR_STX #undef GEN_VR_LVE