diff mbox series

[PULL,29/54] target/ppc: Implement vclzdm/vctzdm instructions

Message ID 20211109055204.230765-30-david@gibson.dropbear.id.au (mailing list archive)
State New, archived
Headers show
Series [PULL,01/54] target/ppc: introduce do_ea_calc | expand

Commit Message

David Gibson Nov. 9, 2021, 5:51 a.m. UTC 
From: Matheus Ferst <matheus.ferst@eldorado.org.br>

The signature of do_cntzdm is changed to allow reuse as GVecGen3i.fni8.
The method is also moved out of #ifdef TARGET_PPC64, as PowerISA doesn't
say vclzdm and vctzdm are 64-bit only.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-3-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 target/ppc/insn32.decode                   |  2 ++
 target/ppc/translate/fixedpoint-impl.c.inc |  4 +--
 target/ppc/translate/vmx-impl.c.inc        | 32 ++++++++++++++++++++++
 3 files changed, 35 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 65075f0d03..6ce06b231d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -334,3 +334,5 @@  DSCRIQ          111111 ..... ..... ...... 001100010 .   @Z22_tap_sh_rc
 ## Vector Bit Manipulation Instruction
 
 VCFUGED         000100 ..... ..... ..... 10101001101    @VX
+VCLZDM          000100 ..... ..... ..... 11110000100    @VX
+VCTZDM          000100 ..... ..... ..... 11111000100    @VX
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index fa519c2d3e..e093562e2a 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -414,8 +414,7 @@  static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
     return true;
 }
 
-#if defined(TARGET_PPC64)
-static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
+static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, int64_t trail)
 {
     TCGv_i64 tmp;
     TCGLabel *l1;
@@ -444,7 +443,6 @@  static void do_cntzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask, bool trail)
 
     tcg_gen_mov_i64(dst, tmp);
 }
-#endif
 
 static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
 {
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index e36c66589c..6da8a9123f 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1575,6 +1575,38 @@  static bool trans_VCFUGED(DisasContext *ctx, arg_VX *a)
     return true;
 }
 
+static bool trans_VCLZDM(DisasContext *ctx, arg_VX *a)
+{
+    static const GVecGen3i g = {
+        .fni8 = do_cntzdm,
+        .vece = MO_64,
+    };
+
+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+    REQUIRE_VECTOR(ctx);
+
+    tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+                    avr_full_offset(a->vrb), 16, 16, false, &g);
+
+    return true;
+}
+
+static bool trans_VCTZDM(DisasContext *ctx, arg_VX *a)
+{
+    static const GVecGen3i g = {
+        .fni8 = do_cntzdm,
+        .vece = MO_64,
+    };
+
+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+    REQUIRE_VECTOR(ctx);
+
+    tcg_gen_gvec_3i(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+                    avr_full_offset(a->vrb), 16, 16, true, &g);
+
+    return true;
+}
+
 #undef GEN_VR_LDX
 #undef GEN_VR_STX
 #undef GEN_VR_LVE