From patchwork Tue Nov 9 05:51:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 12609801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21B35C433EF for ; Tue, 9 Nov 2021 06:43:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B859961105 for ; Tue, 9 Nov 2021 06:43:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B859961105 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:60710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mkKqi-0007tV-E8 for qemu-devel@archiver.kernel.org; Tue, 09 Nov 2021 01:43:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkK4S-0005HT-5G; Tue, 09 Nov 2021 00:53:24 -0500 Received: from gandalf.ozlabs.org ([150.107.74.76]:44449) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mkK4N-0006uB-JC; Tue, 09 Nov 2021 00:53:23 -0500 Received: by gandalf.ozlabs.org (Postfix, from userid 1007) id 4HpHDp5702z4xfJ; Tue, 9 Nov 2021 16:52:10 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gibson.dropbear.id.au; s=201602; t=1636437130; bh=UaKtNBcwHdcJj7GSlketdtVx+mrQ+e2TY8Gu0IoKbzs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=moEhczqalG3Yy5yn/HgFkd3rWho5gjjnrXxTTrXlivBRNUuIJo1hnA+ADxuDbKOr9 /n9RqdT6Oouzarr/6zCZL/uabfXpN5+itbtKjgCFh64c1hEJVQgEY85oXkY+sk14cy 4hHLzpi14d+756fpm5ZnYIPwquSTjSU2KzteSZDI= From: David Gibson To: peter.maydell@linaro.org, clg@kaod.org, danielhb413@gmail.com, groug@kaod.org Subject: [PULL 39/54] target/ppc: moved stxv and lxv from legacy to decodtree Date: Tue, 9 Nov 2021 16:51:49 +1100 Message-Id: <20211109055204.230765-40-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211109055204.230765-1-david@gibson.dropbear.id.au> References: <20211109055204.230765-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Received-SPF: pass client-ip=150.107.74.76; envelope-from=dgibson@gandalf.ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Lucas Mateus Castro \(alqotel\)" , Richard Henderson , qemu-devel@nongnu.org, Luis Pires , qemu-ppc@nongnu.org, Matheus Ferst , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Lucas Mateus Castro (alqotel)" Moved stxv and lxv implementation from the legacy system to decodetree. Reviewed-by: Richard Henderson Signed-off-by: Luis Pires Signed-off-by: Lucas Mateus Castro (alqotel) Signed-off-by: Matheus Ferst Message-Id: <20211104123719.323713-13-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson --- target/ppc/insn32.decode | 8 +++++ target/ppc/translate.c | 17 ++-------- target/ppc/translate/vsx-impl.c.inc | 51 +++++++++++++++++++++++++++-- 3 files changed, 59 insertions(+), 17 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index e438177b32..296d6d6c5a 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -28,6 +28,9 @@ %dq_rtp 22:4 !function=times_2 @DQ_rtp ...... ....0 ra:5 ............ .... &D rt=%dq_rtp si=%dq_si +%dq_rt_tsx 3:1 21:5 +@DQ_TSX ...... ..... ra:5 ............ .... &D si=%dq_si rt=%dq_rt_tsx + %ds_si 2:s14 !function=times_4 @DS ...... rt:5 ra:5 .............. .. &D si=%ds_si @@ -385,3 +388,8 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN + +# VSX Load/Store Instructions + +LXV 111101 ..... ..... ............ . 001 @DQ_TSX +STXV 111101 ..... ..... ............ . 101 @DQ_TSX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index e88b613093..9960df6e18 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7446,20 +7446,7 @@ static void gen_dform39(DisasContext *ctx) /* handles stfdp, lxv, stxsd, stxssp lxvx */ static void gen_dform3D(DisasContext *ctx) { - if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ - switch (ctx->opcode & 0x7) { - case 1: /* lxv */ - if (ctx->insns_flags2 & PPC2_ISA300) { - return gen_lxv(ctx); - } - break; - case 5: /* stxv */ - if (ctx->insns_flags2 & PPC2_ISA300) { - return gen_stxv(ctx); - } - break; - } - } else { /* DS-FORM */ + if ((ctx->opcode & 3) != 1) { /* DS-FORM */ switch (ctx->opcode & 0x3) { case 0: /* stfdp */ if (ctx->insns_flags2 & PPC2_ISA205) { @@ -7584,7 +7571,7 @@ GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000, #endif /* handles lfdp, lxsd, lxssp */ GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), -/* handles stfdp, lxv, stxsd, stxssp, stxv */ +/* handles stfdp, stxsd, stxssp */ GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index d923c6a090..9da66b5348 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -307,7 +307,6 @@ static void gen_##name(DisasContext *ctx) \ tcg_temp_free_i64(xtl); \ } -VSX_VECTOR_LOAD(lxv, ld_i64, 0) VSX_VECTOR_LOAD(lxvx, ld_i64, 1) #define VSX_VECTOR_STORE(name, op, indexed) \ @@ -360,7 +359,6 @@ static void gen_##name(DisasContext *ctx) \ tcg_temp_free_i64(xtl); \ } -VSX_VECTOR_STORE(stxv, st_i64, 0) VSX_VECTOR_STORE(stxvx, st_i64, 1) #ifdef TARGET_PPC64 @@ -2052,6 +2050,55 @@ static void gen_xvxsigdp(DisasContext *ctx) tcg_temp_free_i64(xbl); } +static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ, + int rt, bool store) +{ + TCGv ea; + TCGv_i64 xt; + MemOp mop; + + xt = tcg_temp_new_i64(); + + mop = DEF_MEMOP(MO_Q); + + gen_set_access_type(ctx, ACCESS_INT); + ea = do_ea_calc(ctx, ra, displ); + + if (store) { + get_cpu_vsr(xt, rt, !ctx->le_mode); + tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop); + gen_addr_add(ctx, ea, ea, 8); + get_cpu_vsr(xt, rt, ctx->le_mode); + tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop); + } else { + tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop); + set_cpu_vsr(rt, xt, !ctx->le_mode); + gen_addr_add(ctx, ea, ea, 8); + tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop); + set_cpu_vsr(rt, xt, ctx->le_mode); + } + + tcg_temp_free(ea); + tcg_temp_free_i64(xt); + return true; +} + +static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA300); + + if (a->rt >= 32) { + REQUIRE_VSX(ctx); + } else { + REQUIRE_VECTOR(ctx); + } + + return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store); +} + +TRANS(STXV, do_lstxv_D, true) +TRANS(LXV, do_lstxv_D, false) + #undef GEN_XX2FORM #undef GEN_XX3FORM #undef GEN_XX2IFORM