From patchwork Sun Nov 14 10:56:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 12617853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4AEFC433F5 for ; Sun, 14 Nov 2021 10:57:43 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6CECE61077 for ; Sun, 14 Nov 2021 10:57:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6CECE61077 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=csgraf.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:38480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mmDCg-0007lP-HH for qemu-devel@archiver.kernel.org; Sun, 14 Nov 2021 05:57:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:49434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mmDBz-0006fT-Cq; Sun, 14 Nov 2021 05:56:59 -0500 Received: from mail.csgraf.de ([85.25.223.15]:39320 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mmDBu-00034M-Gr; Sun, 14 Nov 2021 05:56:58 -0500 Received: from localhost.localdomain (dynamic-095-118-029-131.95.118.pool.telefonica.de [95.118.29.131]) by csgraf.de (Postfix) with ESMTPSA id 27F376080090; Sun, 14 Nov 2021 11:56:46 +0100 (CET) From: Alexander Graf To: qemu-arm@nongnu.org Subject: [PATCH] arm: Don't remove EL3 exposure for SMC conduit Date: Sun, 14 Nov 2021 11:56:45 +0100 Message-Id: <20211114105645.16841-1-agraf@csgraf.de> X-Mailer: git-send-email 2.30.1 (Apple Git-130) MIME-Version: 1.0 Received-SPF: pass client-ip=85.25.223.15; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell , Richard Henderson , qemu-devel@nongnu.org, Andrei Warkentin Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" When we expose an SMC conduit, we're implicitly telling the guest that there is EL3 available because it needs to call it. While that EL3 then is not backed by the emulated CPU, from the guest's EL2 point of view, it still means there is an EL3 to call into. This is a problem for VMware ESXi, which validates EL3 availability before doing SMC calls. With this patch, VMware ESXi works with SMP in TCG. Reported-by: Andrei Warkentin Signed-off-by: Alexander Graf --- target/arm/cpu.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a211804fd3..21092c5242 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1782,11 +1782,21 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) */ unset_feature(env, ARM_FEATURE_EL3); - /* Disable the security extension feature bits in the processor feature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. - */ - cpu->isar.id_pfr1 &= ~0xf0; - cpu->isar.id_aa64pfr0 &= ~0xf000; + if (cpu->psci_conduit == QEMU_PSCI_CONDUIT_SMC) { + /* + * We tell the guest to use SMC calls into EL3 for PSCI calls, so + * there has to be EL3 available. We merely execute it on the host + * in QEMU rather than in actual EL3 inside the guest. + */ + } else { + /* + * Disable the security extension feature bits in the processor + * feature registers as well. These are id_pfr1[7:4] and + * id_aa64pfr0[15:12]. + */ + cpu->isar.id_pfr1 &= ~0xf0; + cpu->isar.id_aa64pfr0 &= ~0xf000; + } } if (!cpu->has_el2) {