diff mbox series

[15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns

Message ID 20211229023348.12606-16-frank.chang@sifive.com (mailing list archive)
State New, archived
Headers show
Series Add RISC-V RVV Zve32f and Zve64f extensions | expand

Commit Message

Frank Chang Dec. 29, 2021, 2:33 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

Vector widening conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

Comments

Alistair Francis Jan. 17, 2022, 10:56 p.m. UTC | #1 
On Wed, Dec 29, 2021 at 12:50 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Vector widening conversion instructions are provided to and from all
> supported integer EEWs for Zve32f extension.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index c3f4dabf36..da0e501f85 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -77,6 +77,17 @@ static bool require_zve32f(DisasContext *s)
>      return s->ext_zve32f ? s->sew <= MO_32 : true;
>  }
>
> +static bool require_scale_zve32f(DisasContext *s)
> +{
> +    /* RVV + Zve32f = RVV. */
> +    if (has_ext(s, RVV)) {
> +        return true;
> +    }
> +
> +    /* Zve32f doesn't support FP64. (Section 18.2) */
> +    return s->ext_zve64f ? s->sew <= MO_16 : true;
> +}
> +
>  static bool require_zve64f(DisasContext *s)
>  {
>      /* RVV + Zve64f = RVV. */
> @@ -2356,6 +2367,7 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
>             (s->sew != MO_8) &&
>             vext_check_isa_ill(s) &&
>             vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +           require_scale_zve32f(s) &&
>             require_scale_zve64f(s);
>  }
>
> @@ -2396,6 +2408,7 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
>             (s->sew != MO_8) &&
>             vext_check_isa_ill(s) &&
>             vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> +           require_scale_zve32f(s) &&
>             require_scale_zve64f(s);
>  }
>
> @@ -2427,6 +2440,7 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
>             (s->sew != MO_8) &&
>             vext_check_isa_ill(s) &&
>             vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
> +           require_scale_zve32f(s) &&
>             require_scale_zve64f(s);
>  }
>
> @@ -2467,6 +2481,7 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
>             (s->sew != MO_8) &&
>             vext_check_isa_ill(s) &&
>             vext_check_dd(s, a->rd, a->rs2, a->vm) &&
> +           require_scale_zve32f(s) &&
>             require_scale_zve64f(s);
>  }
>
> @@ -2731,6 +2746,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
>  {
>      return opfv_widen_check(s, a) &&
>             require_rvf(s) &&
> +           require_zve32f(s) &&
>             require_zve64f(s);
>  }
>
> @@ -2739,6 +2755,7 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
>      return opfv_widen_check(s, a) &&
>             require_scale_rvf(s) &&
>             (s->sew != MO_8) &&
> +           require_scale_zve32f(s) &&
>             require_scale_zve64f(s);
>  }
>
> @@ -2791,6 +2808,7 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
>             vext_check_isa_ill(s) &&
>             /* OPFV widening instructions ignore vs1 check */
>             vext_check_ds(s, a->rd, a->rs2, a->vm) &&
> +           require_scale_zve32f(s) &&
>             require_scale_zve64f(s);
>  }
>
> --
> 2.31.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index c3f4dabf36..da0e501f85 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -77,6 +77,17 @@  static bool require_zve32f(DisasContext *s)
     return s->ext_zve32f ? s->sew <= MO_32 : true;
 }
 
+static bool require_scale_zve32f(DisasContext *s)
+{
+    /* RVV + Zve32f = RVV. */
+    if (has_ext(s, RVV)) {
+        return true;
+    }
+
+    /* Zve32f doesn't support FP64. (Section 18.2) */
+    return s->ext_zve64f ? s->sew <= MO_16 : true;
+}
+
 static bool require_zve64f(DisasContext *s)
 {
     /* RVV + Zve64f = RVV. */
@@ -2356,6 +2367,7 @@  static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2396,6 +2408,7 @@  static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2427,6 +2440,7 @@  static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2467,6 +2481,7 @@  static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
            (s->sew != MO_8) &&
            vext_check_isa_ill(s) &&
            vext_check_dd(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2731,6 +2746,7 @@  static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
 {
     return opfv_widen_check(s, a) &&
            require_rvf(s) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -2739,6 +2755,7 @@  static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
     return opfv_widen_check(s, a) &&
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2791,6 +2808,7 @@  static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
            vext_check_isa_ill(s) &&
            /* OPFV widening instructions ignore vs1 check */
            vext_check_ds(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }