diff mbox series

[16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns

Message ID 20211229023348.12606-17-frank.chang@sifive.com (mailing list archive)
State New, archived
Headers show
Series Add RISC-V RVV Zve32f and Zve64f extensions | expand

Commit Message

Frank Chang Dec. 29, 2021, 2:33 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

Vector narrowing conversion instructions are provided to and from all
supported integer EEWs for Zve32f extension.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
 1 file changed, 3 insertions(+)

Comments

Alistair Francis Jan. 17, 2022, 10:57 p.m. UTC | #1 
On Wed, Dec 29, 2021 at 12:46 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Vector narrowing conversion instructions are provided to and from all
> supported integer EEWs for Zve32f extension.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvv.c.inc | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index da0e501f85..5214cf08db 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -2860,6 +2860,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
>      return opfv_narrow_check(s, a) &&
>             require_rvf(s) &&
>             (s->sew != MO_64) &&
> +           require_zve32f(s) &&
>             require_zve64f(s);
>  }
>
> @@ -2868,6 +2869,7 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
>      return opfv_narrow_check(s, a) &&
>             require_scale_rvf(s) &&
>             (s->sew != MO_8) &&
> +           require_scale_zve32f(s) &&
>             require_scale_zve64f(s);
>  }
>
> @@ -2918,6 +2920,7 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
>             vext_check_isa_ill(s) &&
>             /* OPFV narrowing instructions ignore vs1 check */
>             vext_check_sd(s, a->rd, a->rs2, a->vm) &&
> +           require_scale_zve32f(s) &&
>             require_scale_zve64f(s);
>  }
>
> --
> 2.31.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index da0e501f85..5214cf08db 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2860,6 +2860,7 @@  static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
     return opfv_narrow_check(s, a) &&
            require_rvf(s) &&
            (s->sew != MO_64) &&
+           require_zve32f(s) &&
            require_zve64f(s);
 }
 
@@ -2868,6 +2869,7 @@  static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
     return opfv_narrow_check(s, a) &&
            require_scale_rvf(s) &&
            (s->sew != MO_8) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }
 
@@ -2918,6 +2920,7 @@  static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
            vext_check_isa_ill(s) &&
            /* OPFV narrowing instructions ignore vs1 check */
            vext_check_sd(s, a->rd, a->rs2, a->vm) &&
+           require_scale_zve32f(s) &&
            require_scale_zve64f(s);
 }