| Message ID | 20211230123539.52786-2-anup@brainfault.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU RISC-V AIA support | expand |
Anup Patel <anup@brainfault.org> 於 2021年12月30日 週四 下午8:37寫道： > From: Anup Patel <anup.patel@wdc.com> > > We should be returning illegal instruction trap when RV64 HS-mode tries > to access RV32 HS-mode CSR. > > Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Signed-off-by: Anup Patel <anup@brainfault.org> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > --- > target/riscv/csr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 146447eac5..fd7110c38b 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -182,7 +182,7 @@ static RISCVException hmode(CPURISCVState *env, int > csrno) > static RISCVException hmode32(CPURISCVState *env, int csrno) > { > if (riscv_cpu_mxl(env) != MXL_RV32) { > - if (riscv_cpu_virt_enabled(env)) { > + if (!riscv_cpu_virt_enabled(env)) { > return RISCV_EXCP_ILLEGAL_INST; > } else { > return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > -- > 2.25.1 > > > Reviewed-by: Frank Chang <frank.chang@sifive.com>
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 146447eac5..fd7110c38b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -182,7 +182,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno) { if (riscv_cpu_mxl(env) != MXL_RV32) { - if (riscv_cpu_virt_enabled(env)) { + if (!riscv_cpu_virt_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } else { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;