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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id x19sm193593pgi.19.2022.01.04.18.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jan 2022 18:22:55 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v2 1/3] target/riscv: rvv-1.0: Call the correct RVF/RVD check function for widening fp insns Date: Wed, 5 Jan 2022 10:22:44 +0800 Message-Id: <20220105022247.21131-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220105022247.21131-1-frank.chang@sifive.com> References: <20220105022247.21131-1-frank.chang@sifive.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1036 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1036.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Palmer Dabbelt , Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Vector widening floating-point instructions should use require_scale_rvf() instead of require_rvf() to check whether RVF/RVD is enabled. Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5e3f7fdb77..8d92243f2b 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2254,7 +2254,8 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check) static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && - require_rvf(s) && + require_scale_rvf(s) && + (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); } @@ -2292,7 +2293,8 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check) static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && - require_rvf(s) && + require_scale_rvf(s) && + (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_ds(s, a->rd, a->rs2, a->vm); } @@ -2321,7 +2323,8 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && - require_rvf(s) && + require_scale_rvf(s) && + (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); } @@ -2359,7 +2362,8 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv) static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && - require_rvf(s) && + require_scale_rvf(s) && + (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dd(s, a->rd, a->rs2, a->vm); }