From patchwork Thu Jan 13 20:20:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 12713118 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94D65C4332F for ; Thu, 13 Jan 2022 20:22:48 +0000 (UTC) Received: from localhost ([::1]:37360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n86cR-000607-Gr for qemu-devel@archiver.kernel.org; Thu, 13 Jan 2022 15:22:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n86aj-0003r5-Oy for qemu-devel@nongnu.org; Thu, 13 Jan 2022 15:21:01 -0500 Received: from [2a00:1450:4864:20::12a] (port=36449 helo=mail-lf1-x12a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n86af-0004Ji-Q4 for qemu-devel@nongnu.org; Thu, 13 Jan 2022 15:21:01 -0500 Received: by mail-lf1-x12a.google.com with SMTP id b14so5112978lff.3 for ; Thu, 13 Jan 2022 12:20:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oQR/XB8xlMCe6WSfiop7OtVpoj5mhOGrn883baEJoJk=; b=OCNQPhv30wP5f5OkOCh1Ff3rV897kgaJrHUpSZFwv0QYRPuFJaRFR/LtM95QPJqppd uI3JMnmCZKCwXdynKLiJwcPKY4+X1xH45040ZZFQFtwgkNdqnwYJVE6RPZOdaAlejtdX ZL04fnTNzohtwe5czvwP+q6rGaCcaFHkQNyASGCykOMCvYrVTFnoi00qMO5pBQErhRBW LCbMZVdmRj5LpPo09Sv0tTgjR+6nzj9kEzNcn0T3DEu3m8nLgfQeEZ+TJsxaktxIU0cQ Xq/oXCQaTPPoJXEPD1XAI+rWYcUe8XKveHPof14/s0XkOs5tBpfcV7UA72zBIC4J4nFc lv/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oQR/XB8xlMCe6WSfiop7OtVpoj5mhOGrn883baEJoJk=; b=OPIXne4YiU6wty0ts5iJB+wIIEFKPpysAKZWkr9i/CuQJP1vZyBKQ5DvNmdu6XGVYc EcW8depC3uYkYX9AuZmd/Nb3KjbNt7Gl/np7hTq9owqzJxLQ3XLf45s/+tmfp/V+R+aU QPBAYbIfEQ/abt+0KrwnqCC0jUT9JsUgHUht+7nMzNm0KqUMxsdJf+9UIjtAj++ck1bn 08RW/Sh96Btm1EQU9YUEx1FGLQqa9UyXgU+hqBDAe6A6DaNWDuAiHrWOzDrZY9pHBFgk ptxPjKgM1pAEagn6Z7wdt5RDO1L1b5ELy5+KoGl2qgKHA6hVozbHQ1L6PKtrEvanFpkJ iPZw== X-Gm-Message-State: AOAM53375+u5aYXy489SYkbrYmFXdgF7u2aRnfuNnKVMFWhyTEVQtM2C LqF945NQ+3d3OUZ2kY6HiCSReLBFyGPaI2pw X-Google-Smtp-Source: ABdhPJyJf85A/0G+iOqaXXXRKdzLPwL9i3p17crDVo4oWg+mHcMJCFNcSMRkPWkbFoE/oREXazePBg== X-Received: by 2002:a19:ae1a:: with SMTP id f26mr4461481lfc.270.1642105245514; Thu, 13 Jan 2022 12:20:45 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id h23sm371872ljk.9.2022.01.13.12.20.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Jan 2022 12:20:44 -0800 (PST) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension Date: Thu, 13 Jan 2022 21:20:33 +0100 Message-Id: <20220113202033.3320854-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220113202033.3320854-1-philipp.tomsich@vrull.eu> References: <20220113202033.3320854-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::12a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x12a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Bin Meng , Philipp Tomsich , Greg Favor , Palmer Dabbelt , Alistair Francis , Kito Cheng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This adds the decoder and translation for the XVentanaCondOps custom extension (vendor-defined by Ventana Micro Systems), which is documented at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf This commit then also adds a guard-function (has_XVentanaCondOps_p) and the decoder function to the table of decoders, enabling the support for the XVentanaCondOps extension. Signed-off-by: Philipp Tomsich --- Changes in v2: - Split off decode table into XVentanaCondOps.decode - Wire up XVentanaCondOps in the decoder-table target/riscv/XVentanaCondOps.decode | 25 ++++++++++++ target/riscv/cpu.c | 3 ++ target/riscv/cpu.h | 3 ++ .../insn_trans/trans_xventanacondops.inc | 39 +++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 13 +++++++ 6 files changed, 84 insertions(+) create mode 100644 target/riscv/XVentanaCondOps.decode create mode 100644 target/riscv/insn_trans/trans_xventanacondops.inc diff --git a/target/riscv/XVentanaCondOps.decode b/target/riscv/XVentanaCondOps.decode new file mode 100644 index 0000000000..5aef7c3d72 --- /dev/null +++ b/target/riscv/XVentanaCondOps.decode @@ -0,0 +1,25 @@ +# +# RISC-V translation routines for the XVentanaCondOps extension +# +# Copyright (c) 2022 Dr. Philipp Tomsich, philipp.tomsich@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Reference: VTx-family custom instructions +# Custom ISA extensions for Ventana Micro Systems RISC-V cores +# (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf) + +# Fields +%rs2 20:5 +%rs1 15:5 +%rd 7:5 + +# Argument sets +&r rd rs1 rs2 !extern + +# Formats +@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd + +# *** RV64 Custom-3 Extension *** +vt_maskc 0000000 ..... ..... 110 ..... 1111011 @r +vt_maskcn 0000000 ..... ..... 111 ..... 1111011 @r diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9bc25d3055..fc8ab1dc2b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -673,6 +673,9 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), + /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d63086765..ffde94fd1a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -330,6 +330,9 @@ struct RISCVCPU { bool ext_zfh; bool ext_zfhmin; + /* Vendor-specific custom extensions */ + bool ext_XVentanaCondOps; + char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/insn_trans/trans_xventanacondops.inc b/target/riscv/insn_trans/trans_xventanacondops.inc new file mode 100644 index 0000000000..b8a5d031b5 --- /dev/null +++ b/target/riscv/insn_trans/trans_xventanacondops.inc @@ -0,0 +1,39 @@ +/* + * RISC-V translation routines for the XVentanaCondOps extension. + * + * Copyright (c) 2021-2022 VRULL GmbH. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +static bool gen_condmask(DisasContext *ctx, arg_r *a, TCGCond cond) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero); + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +static bool trans_vt_maskc(DisasContext *ctx, arg_r *a) +{ + return gen_condmask(ctx, a, TCG_COND_NE); +} + +static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a) +{ + return gen_condmask(ctx, a, TCG_COND_EQ); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index a32158da93..1f3a15398b 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -4,6 +4,7 @@ dir = meson.current_source_dir() gen = [ decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']), decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'), + decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'), ] riscv_ss = ss.source_set() diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2cbf9cbb6f..efdf8a7bdb 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -122,6 +122,15 @@ static inline bool always_true_p(CPURISCVState *env __attribute__((__unused__)) return true; } +#define MATERIALISE_EXT_PREDICATE(ext) \ + static inline bool has_ ## ext ## _p(CPURISCVState *env, \ + DisasContext *ctx __attribute__((__unused__))) \ + { \ + return RISCV_CPU(ctx->cs)->cfg.ext_ ## ext ; \ + } + +MATERIALISE_EXT_PREDICATE(XVentanaCondOps); + #ifdef TARGET_RISCV32 #define get_xl(ctx) MXL_RV32 #elif defined(CONFIG_USER_ONLY) @@ -844,9 +853,12 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvb.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_privileged.c.inc" +#include "insn_trans/trans_xventanacondops.inc" /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" +/* Include decoders for factored-out extensions */ +#include "decode-XVentanaCondOps.c.inc" static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { @@ -862,6 +874,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) bool (*decode_func)(DisasContext *, uint32_t); } decoders[] = { { always_true_p, decode_insn32 }, + { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; /* Check for compressed insn */