From patchwork Mon Jan 17 13:28:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12715490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 846D1C433FE for ; Mon, 17 Jan 2022 14:34:27 +0000 (UTC) Received: from localhost ([::1]:46420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1n9T5W-00042A-5s for qemu-devel@archiver.kernel.org; Mon, 17 Jan 2022 09:34:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38536) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1n9S5D-0001Jh-B4 for qemu-devel@nongnu.org; Mon, 17 Jan 2022 08:30:03 -0500 Received: from [2607:f8b0:4864:20::536] (port=36745 helo=mail-pg1-x536.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1n9S58-0000fg-PC for qemu-devel@nongnu.org; Mon, 17 Jan 2022 08:30:03 -0500 Received: by mail-pg1-x536.google.com with SMTP id e9so374500pgb.3 for ; Mon, 17 Jan 2022 05:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=et/vu/jUQE/J1fBuabFyLO2+T/t14yfVAc9Ry0i324A=; b=mXSD7tfcj6DbAeUcRl7p0MC2Jv8gCQRdFUmwg6VgogdsWYIHm+siDHVhrbx4Mdt9Qu kOnfaMiEyFATkRDBlvVt28JpAUpfuSw9VhHbmU7oarGB+uj74FRP04mgjfAM/453zB/5 BRZ12Fn/MIeYHbEwmbS0jJyC+z7Wu9M75tdimqq4/46FqFJfGmIS2JDl/vXKGAcSRreg bmykfJ014T4r3QbGZYhLtPU8xgbGMdeu67CQtYlvU+5FeB64MclBGZ3oI5OydZ8k00Up QutZy4GdAEsR4WheHu8pkdH4UoXckIEyU3EStlBnNjmioYBEUDn31iyA1PIcC3faq2kn 1Gqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=et/vu/jUQE/J1fBuabFyLO2+T/t14yfVAc9Ry0i324A=; b=t+K9lYv3fXYjik7QzPZ3rAfH4uHk6jFv6x7xFa4GaTRjP83tZpgs8svYdUFgHxlTKV 7B28VWkvMzoYVufEf2sPI+ALWwNOBinJiaPh/wpPYN3BjBBbt79wMXvvU6FXJYbIx/Qc 2hFdpjVUbeUb4AhCCH9xFIOBOBF3zvLCbJaU5IwwG2CFPKAWzaWpP0GcPzbSQArmmg3W bMP4dJSYysoDqgkPk7okOfE5h2a8HyTRcxCZ5uBZL6byrpxU7UYsdEIN/JHBlZ1Vlh/m f0bOeHWQASemNXehK03w2E6dX0S1ZWQH0hyC2ADrohoVpYdKUr+k1A0iVgSt5b31jgWE 710Q== X-Gm-Message-State: AOAM531mekblYsfQqjcrdb+jzwUMxPwf5l3gafFuRaEwTxJsWUmqLZjQ DH+O7pgOV6VylEXkYWcBtpwbQA== X-Google-Smtp-Source: ABdhPJy+O3r35E87/OIpDKCuMUDkNOWXGE3w0oIsM1Nnw95Ra0GdT2bn9DLLVfgK3QLLOc+ebkmKeQ== X-Received: by 2002:a63:90c8:: with SMTP id a191mr19579561pge.622.1642426186939; Mon, 17 Jan 2022 05:29:46 -0800 (PST) Received: from localhost.localdomain ([122.179.70.109]) by smtp.gmail.com with ESMTPSA id 7sm9532607pfm.25.2022.01.17.05.29.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 05:29:46 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v7 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback Date: Mon, 17 Jan 2022 18:58:11 +0530 Message-Id: <20220117132826.426418-9-anup@brainfault.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220117132826.426418-1-anup@brainfault.org> References: <20220117132826.426418-1-anup@brainfault.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::536 (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::536; envelope-from=anup@brainfault.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Anup Patel , qemu-devel@nongnu.org, Alistair Francis , Atish Patra , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.h | 23 +++++++++++++++++++++++ target/riscv/cpu_helper.c | 14 ++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 71a2fd1da7..cee70f8608 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -254,6 +254,22 @@ struct CPURISCVState { uint64_t (*rdtime_fn)(uint32_t); uint32_t rdtime_fn_arg; + /* machine specific AIA ireg read-modify-write callback */ +#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ + ((((__xlen) & 0xff) << 24) | \ + (((__vgein) & 0x3f) << 20) | \ + (((__virt) & 0x1) << 18) | \ + (((__priv) & 0x3) << 16) | \ + (__isel & 0xffff)) +#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) +#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) +#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) +#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) +#define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) + int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, + target_ulong *val, target_ulong new_val, target_ulong write_mask); + void *aia_ireg_rmw_fn_arg[4]; + /* True if in debugger mode. */ bool debugger; @@ -410,6 +426,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), uint32_t arg); +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, + int (*rmw_fn)(void *arg, + target_ulong reg, + target_ulong *val, + target_ulong new_val, + target_ulong write_mask), + void *rmw_fn_arg); #endif void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 01a8baea06..59c8f900df 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -395,6 +395,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), env->rdtime_fn_arg = arg; } +void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, + int (*rmw_fn)(void *arg, + target_ulong reg, + target_ulong *val, + target_ulong new_val, + target_ulong write_mask), + void *rmw_fn_arg) +{ + if (priv <= PRV_M) { + env->aia_ireg_rmw_fn[priv] = rmw_fn; + env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg; + } +} + void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) { if (newpriv > PRV_M) {