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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id c12sm8286136pfm.113.2022.01.17.17.46.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jan 2022 17:46:20 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns Date: Tue, 18 Jan 2022 09:45:19 +0800 Message-Id: <20220118014522.13613-17-frank.chang@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220118014522.13613-1-frank.chang@sifive.com> References: <20220118014522.13613-1-frank.chang@sifive.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Vector narrowing conversion instructions are provided to and from all supported integer EEWs for Zve32f extension. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index f2d3c9e8b9..7a040b3089 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2862,6 +2862,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) return opfv_narrow_check(s, a) && require_rvf(s) && (s->sew != MO_64) && + require_zve32f(s) && require_zve64f(s); } @@ -2870,6 +2871,7 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) return opfv_narrow_check(s, a) && require_scale_rvf(s) && (s->sew != MO_8) && + require_scale_zve32f(s) && require_scale_zve64f(s); } @@ -2920,6 +2922,7 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) vext_check_isa_ill(s) && /* OPFV narrowing instructions ignore vs1 check */ vext_check_sd(s, a->rd, a->rs2, a->vm) && + require_scale_zve32f(s) && require_scale_zve64f(s); }