[v8,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

Commit Message

Anup Patel Jan. 19, 2022, 3:25 p.m. UTC

From: Anup Patel <[e-mail]>

We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.

Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel <[e-mail]>
Signed-off-by: Anup Patel <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
Reviewed-by: Bin Meng <[e-mail]>
Reviewed-by: Frank Chang <[e-mail]>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a9e7ac903b..f7f178b63b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -186,7 +186,7 @@  static RISCVException hmode(CPURISCVState *env, int csrno)
 static RISCVException hmode32(CPURISCVState *env, int csrno)
 {
     if (riscv_cpu_mxl(env) != MXL_RV32) {
-        if (riscv_cpu_virt_enabled(env)) {
+        if (!riscv_cpu_virt_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
         } else {
             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;