[v8,06/23] target/riscv: Add AIA cpu feature

Commit Message

Anup Patel Jan. 19, 2022, 3:25 p.m. UTC

From: Anup Patel <[e-mail]>

We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.

Signed-off-by: Anup Patel <[e-mail]>
Signed-off-by: Anup Patel <[e-mail]>
Reviewed-by: Bin Meng <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
Reviewed-by: Frank Chang <[e-mail]>
---
 target/riscv/cpu.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f24b6963b0..070d741297 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -78,7 +78,8 @@  enum {
     RISCV_FEATURE_MMU,
     RISCV_FEATURE_PMP,
     RISCV_FEATURE_EPMP,
-    RISCV_FEATURE_MISA
+    RISCV_FEATURE_MISA,
+    RISCV_FEATURE_AIA
 };
 
 #define PRIV_VERSION_1_10_0 0x00011000