| Message ID | 20220131110201.2303275-2-philipp.tomsich@vrull.eu (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/riscv: Add XVentanaCondOps and supporting infrastructure changes | expand |
On Mon, Jan 31, 2022 at 9:03 PM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> > Suggested-by: Richard Henderson <richard.henderson@linaro.org> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > --- > > (no changes since v4) > > Changes in v4: > - use a typedef into 'RISCVCPUConfig' (instead of the explicit > 'struct RISCVCPUConfig') to comply with the coding standard > (as suggested in Richard's review of v3) > > Changes in v3: > - (new patch) refactor 'struct RISCVCPUConfig' > > target/riscv/cpu.h | 78 ++++++++++++++++++++++++---------------------- > 1 file changed, 41 insertions(+), 37 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 55635d68d5..1175915c0d 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -303,6 +303,46 @@ struct RISCVCPUClass { > DeviceReset parent_reset; > }; > > +struct RISCVCPUConfig { > + bool ext_i; > + bool ext_e; > + bool ext_g; > + bool ext_m; > + bool ext_a; > + bool ext_f; > + bool ext_d; > + bool ext_c; > + bool ext_s; > + bool ext_u; > + bool ext_h; > + bool ext_j; > + bool ext_v; > + bool ext_zba; > + bool ext_zbb; > + bool ext_zbc; > + bool ext_zbs; > + bool ext_counters; > + bool ext_ifencei; > + bool ext_icsr; > + bool ext_zfh; > + bool ext_zfhmin; > + bool ext_zve32f; > + bool ext_zve64f; > + > + char *priv_spec; > + char *user_spec; > + char *bext_spec; > + char *vext_spec; > + uint16_t vlen; > + uint16_t elen; > + bool mmu; > + bool pmp; > + bool epmp; > + uint64_t resetvec; > +}; > + > +typedef struct RISCVCPUConfig RISCVCPUConfig; > + > /** > * RISCVCPU: > * @env: #CPURISCVState > @@ -320,43 +360,7 @@ struct RISCVCPU { > char *dyn_vreg_xml; > > /* Configuration Settings */ > - struct { > - bool ext_i; > - bool ext_e; > - bool ext_g; > - bool ext_m; > - bool ext_a; > - bool ext_f; > - bool ext_d; > - bool ext_c; > - bool ext_s; > - bool ext_u; > - bool ext_h; > - bool ext_j; > - bool ext_v; > - bool ext_zba; > - bool ext_zbb; > - bool ext_zbc; > - bool ext_zbs; > - bool ext_counters; > - bool ext_ifencei; > - bool ext_icsr; > - bool ext_zfh; > - bool ext_zfhmin; > - bool ext_zve32f; > - bool ext_zve64f; > - > - char *priv_spec; > - char *user_spec; > - char *bext_spec; > - char *vext_spec; > - uint16_t vlen; > - uint16_t elen; > - bool mmu; > - bool pmp; > - bool epmp; > - uint64_t resetvec; > - } cfg; > + RISCVCPUConfig cfg; > }; > > static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) > -- > 2.33.1 > >
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 55635d68d5..1175915c0d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -303,6 +303,46 @@ struct RISCVCPUClass { DeviceReset parent_reset; }; +struct RISCVCPUConfig { + bool ext_i; + bool ext_e; + bool ext_g; + bool ext_m; + bool ext_a; + bool ext_f; + bool ext_d; + bool ext_c; + bool ext_s; + bool ext_u; + bool ext_h; + bool ext_j; + bool ext_v; + bool ext_zba; + bool ext_zbb; + bool ext_zbc; + bool ext_zbs; + bool ext_counters; + bool ext_ifencei; + bool ext_icsr; + bool ext_zfh; + bool ext_zfhmin; + bool ext_zve32f; + bool ext_zve64f; + + char *priv_spec; + char *user_spec; + char *bext_spec; + char *vext_spec; + uint16_t vlen; + uint16_t elen; + bool mmu; + bool pmp; + bool epmp; + uint64_t resetvec; +}; + +typedef struct RISCVCPUConfig RISCVCPUConfig; + /** * RISCVCPU: * @env: #CPURISCVState @@ -320,43 +360,7 @@ struct RISCVCPU { char *dyn_vreg_xml; /* Configuration Settings */ - struct { - bool ext_i; - bool ext_e; - bool ext_g; - bool ext_m; - bool ext_a; - bool ext_f; - bool ext_d; - bool ext_c; - bool ext_s; - bool ext_u; - bool ext_h; - bool ext_j; - bool ext_v; - bool ext_zba; - bool ext_zbb; - bool ext_zbc; - bool ext_zbs; - bool ext_counters; - bool ext_ifencei; - bool ext_icsr; - bool ext_zfh; - bool ext_zfhmin; - bool ext_zve32f; - bool ext_zve64f; - - char *priv_spec; - char *user_spec; - char *bext_spec; - char *vext_spec; - uint16_t vlen; - uint16_t elen; - bool mmu; - bool pmp; - bool epmp; - uint64_t resetvec; - } cfg; + RISCVCPUConfig cfg; }; static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)