From patchwork Fri Feb 4 17:46:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 12735432 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6D73C433F5 for ; Fri, 4 Feb 2022 18:24:49 +0000 (UTC) Received: from localhost ([::1]:54504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nG3GK-0002pW-04 for qemu-devel@archiver.kernel.org; Fri, 04 Feb 2022 13:24:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:38768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nG2gA-00031d-3m for qemu-devel@nongnu.org; Fri, 04 Feb 2022 12:47:27 -0500 Received: from [2a00:1450:4864:20::335] (port=53036 helo=mail-wm1-x335.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nG2g7-0003kK-Jk for qemu-devel@nongnu.org; Fri, 04 Feb 2022 12:47:25 -0500 Received: by mail-wm1-x335.google.com with SMTP id v129so1521074wme.2 for ; Fri, 04 Feb 2022 09:47:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NXC7GLLmEsyikTRoYgJNb69Znup+5XSzek9+wleqbfY=; b=1lb/u14FVlSvbxRg1yq18IDzTQo7EMbZcG/bynPVEiTjf+63ZOEbp0ybUqoQaVaHsr G34IvHVqhg2ecnR98R8Vmsx1p6BDJTeUrJLvQk0X7sND91o+f7DLbrnLrPCQjc+I/OjT h5baSN8g9qpWh861fDBj2vTwbodVqJSAEcAj/uL+zboVSL7Zne+6DLhrzKxe6n7bZHFf l3YYYmiSP3DfLp5KIxmnzeFjPu5rvhGK+uDc3jCcwLFylCa54EgHTQN8bGMoAjCP5n67 DzVMUinf9DSgoqP0pizPKJh9UBG2k9E/+DCekc6IOhPBzDb7n5txlC6gU1p4Q5T6fd69 FEYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NXC7GLLmEsyikTRoYgJNb69Znup+5XSzek9+wleqbfY=; b=muXg4ZZvFv0SjLai58cszPrSyW0XuTXD7TiH/NsLbQv5TkXXdafcIuNq8jFK/Rai7p 3tBTmORByTnvnmiq+BRAmzj6NAXwoMzwxmuKFPSpjB3Voqd8YRs1YAD99tJE243TNzNs LSrDqkDK1S05ZoZHAbGpgEecKL2poaVbzzQQFZCvFA9UFnjOanOQKCx6Bg9g02DipHyE 2dU2T3wU86oRlzY06HUns8zC/4xbWZH8KzlJVcFy0kK0zp8FR2e8JvwpPNM3wTBYzGS3 J8ifIoDkFe1AR8G6r6jqVSeyPRbGK5O79CRZJm5eM+ZejaZiaTBRFygyNyOrvRxKyyZz qTOA== X-Gm-Message-State: AOAM531jiU2dnDqY12U9cfFt8RCP+TVYcspLYehuIAXbCIe6I/Eeuawg 3YrHw7Slvo3d9WbTx1NUTOIOBQ== X-Google-Smtp-Source: ABdhPJwXMekrlUUH9+kSIQAu8/hW+uV+HKhg86gi8ky5bh/dGSSBm+u7oXP+wzxUxEQcR7mz0ZwX3Q== X-Received: by 2002:a05:600c:4141:: with SMTP id h1mr3200551wmm.171.1643996840938; Fri, 04 Feb 2022 09:47:20 -0800 (PST) Received: from localhost.localdomain ([122.167.157.188]) by smtp.gmail.com with ESMTPSA id f13sm11381876wmq.29.2022.02.04.09.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Feb 2022 09:47:20 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v9 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs Date: Fri, 4 Feb 2022 23:16:38 +0530 Message-Id: <20220204174700.534953-3-anup@brainfault.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220204174700.534953-1-anup@brainfault.org> References: <20220204174700.534953-1-anup@brainfault.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::335 (failed) Received-SPF: none client-ip=2a00:1450:4864:20::335; envelope-from=anup@brainfault.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Anup Patel , qemu-devel@nongnu.org, Alistair Francis , Atish Patra , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 18 +++++++++++------- 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1238aabe3f..e1224d26dc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -434,6 +434,7 @@ static void riscv_cpu_reset(DeviceState *dev) } } env->mcause = 0; + env->miclaim = MIP_SGEIP; env->pc = env->resetvec; env->two_stage_lookup = false; /* mmte is supposed to have pm.current hardwired to 1 */ @@ -695,7 +696,7 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); #ifndef CONFIG_USER_ONLY - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); #endif /* CONFIG_USER_ONLY */ } diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7c87433645..e1256a9982 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -540,6 +540,8 @@ typedef enum RISCVException { #define IRQ_S_EXT 9 #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_LOCAL_MAX 16 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) @@ -554,6 +556,7 @@ typedef enum RISCVException { #define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_SGEIP (1 << IRQ_S_GEXT) /* sip masks */ #define SIP_SSIP MIP_SSIP diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 41a533a310..c635ffb089 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -461,12 +461,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS) static const target_ulong delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | - VS_MODE_INTERRUPTS; + HS_MODE_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ @@ -748,7 +749,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno, { env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); if (riscv_has_ext(env, RVH)) { - env->mideleg |= VS_MODE_INTERRUPTS; + env->mideleg |= HS_MODE_INTERRUPTS; } return RISCV_EXCP_NONE; } @@ -764,6 +765,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno, target_ulong val) { env->mie = (env->mie & ~all_ints) | (val & all_ints); + if (!riscv_has_ext(env, RVH)) { + env->mie &= ~MIP_SGEIP; + } return RISCV_EXCP_NONE; } @@ -1110,7 +1114,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno, } if (ret_value) { - *ret_value &= env->mideleg; + *ret_value &= env->mideleg & S_MODE_INTERRUPTS; } return ret; } @@ -1228,7 +1232,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno, write_mask & hvip_writable_mask); if (ret_value) { - *ret_value &= hvip_writable_mask; + *ret_value &= VS_MODE_INTERRUPTS; } return ret; } @@ -1241,7 +1245,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, write_mask & hip_writable_mask); if (ret_value) { - *ret_value &= hip_writable_mask; + *ret_value &= HS_MODE_INTERRUPTS; } return ret; } @@ -1249,14 +1253,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, static RISCVException read_hie(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->mie & VS_MODE_INTERRUPTS; + *val = env->mie & HS_MODE_INTERRUPTS; return RISCV_EXCP_NONE; } static RISCVException write_hie(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); + target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS); return write_mie(env, CSR_MIE, newval); }