diff mbox series

tests/tcg/s390x: Cleanup of mie3 tests.

Message ID 20220301191455.19004-1-dmiller423@gmail.com (mailing list archive)
State New, archived
Headers show
Series tests/tcg/s390x: Cleanup of mie3 tests. | expand

Commit Message

David Miller March 1, 2022, 7:14 p.m. UTC 
Adds clobbers and merges remaining separate asm statements.

Signed-off-by: David Miller <dmiller423@gmail.com>
---
 tests/tcg/s390x/mie3-compl.c | 42 +++++++++++++++++++++++-------------
 tests/tcg/s390x/mie3-mvcrl.c | 12 +++++++----
 tests/tcg/s390x/mie3-sel.c   | 40 ++++++++++++++++++----------------
 3 files changed, 57 insertions(+), 37 deletions(-)

Comments

David Miller March 1, 2022, 8 p.m. UTC | #1 
Please disregard,  v2 sent.

On Tue, Mar 1, 2022 at 2:15 PM David Miller <dmiller423@gmail.com> wrote:

> Adds clobbers and merges remaining separate asm statements.
>
> Signed-off-by: David Miller <dmiller423@gmail.com>
> ---
>  tests/tcg/s390x/mie3-compl.c | 42 +++++++++++++++++++++++-------------
>  tests/tcg/s390x/mie3-mvcrl.c | 12 +++++++----
>  tests/tcg/s390x/mie3-sel.c   | 40 ++++++++++++++++++----------------
>  3 files changed, 57 insertions(+), 37 deletions(-)
>
> diff --git a/tests/tcg/s390x/mie3-compl.c b/tests/tcg/s390x/mie3-compl.c
> index 35649f3b02..85b23a9b7a 100644
> --- a/tests/tcg/s390x/mie3-compl.c
> +++ b/tests/tcg/s390x/mie3-compl.c
> @@ -1,32 +1,44 @@
>  #include <stdint.h>
>
> +
>  #define FbinOp(S, ASM) uint64_t S(uint64_t a, uint64_t b) \
> -{ \
> -    uint64_t res = 0; \
> -    asm ("llihf %[res],801\n" ASM \
> -         : [res]"=&r"(res) : [a]"r"(a), [b]"r"(b) : "cc"); \
> -    return res; \
> +{                       \
> +    uint64_t res = 0;   \
> +asm volatile (          \
> +    "llihf %%r0,801\n"  \
> +    "lg %%r2, %[a]\n"   \
> +    "lg %%r3, %[b]\n"   \
> +    ASM                 \
> +    "stg %%r0, %[res] " \
> +    : [res] "=m" (res)  \
> +    : [a] "m" (a)       \
> +    , [b] "m" (b)       \
> +    : "r0", "r2", "r3"  \
> +);                      \
> +    return res;         \
>  }
>
> +
>  /* AND WITH COMPLEMENT */
> -FbinOp(_ncrk,  ".insn rrf, 0xB9F50000, %[res], %[b], %[a], 0\n")
> -FbinOp(_ncgrk, ".insn rrf, 0xB9E50000, %[res], %[b], %[a], 0\n")
> +FbinOp(_ncrk,  ".insn rrf, 0xB9F50000, %%r0, %%r3, %%r2, 0\n")
> +FbinOp(_ncgrk, ".insn rrf, 0xB9E50000, %%r0, %%r3, %%r2, 0\n")
>
>  /* NAND */
> -FbinOp(_nnrk,  ".insn rrf, 0xB9740000, %[res], %[b], %[a], 0\n")
> -FbinOp(_nngrk, ".insn rrf, 0xB9640000, %[res], %[b], %[a], 0\n")
> +FbinOp(_nnrk,  ".insn rrf, 0xB9740000, %%r0, %%r3, %%r2, 0\n")
> +FbinOp(_nngrk, ".insn rrf, 0xB9640000, %%r0, %%r3, %%r2, 0\n")
>
>  /* NOT XOR */
> -FbinOp(_nxrk,  ".insn rrf, 0xB9770000, %[res], %[b], %[a], 0\n")
> -FbinOp(_nxgrk, ".insn rrf, 0xB9670000, %[res], %[b], %[a], 0\n")
> +FbinOp(_nxrk,  ".insn rrf, 0xB9770000, %%r0, %%r3, %%r2, 0\n")
> +FbinOp(_nxgrk, ".insn rrf, 0xB9670000, %%r0, %%r3, %%r2, 0\n")
>
>  /* NOR */
> -FbinOp(_nork,  ".insn rrf, 0xB9760000, %[res], %[b], %[a], 0\n")
> -FbinOp(_nogrk, ".insn rrf, 0xB9660000, %[res], %[b], %[a], 0\n")
> +FbinOp(_nork,  ".insn rrf, 0xB9760000, %%r0, %%r3, %%r2, 0\n")
> +FbinOp(_nogrk, ".insn rrf, 0xB9660000, %%r0, %%r3, %%r2, 0\n")
>
>  /* OR WITH COMPLEMENT */
> -FbinOp(_ocrk,  ".insn rrf, 0xB9750000, %[res], %[b], %[a], 0\n")
> -FbinOp(_ocgrk, ".insn rrf, 0xB9650000, %[res], %[b], %[a], 0\n")
> +FbinOp(_ocrk,  ".insn rrf, 0xB9750000, %%r0, %%r3, %%r2, 0\n")
> +FbinOp(_ocgrk, ".insn rrf, 0xB9650000, %%r0, %%r3, %%r2, 0\n")
> +
>
>  int main(int argc, char *argv[])
>  {
> diff --git a/tests/tcg/s390x/mie3-mvcrl.c b/tests/tcg/s390x/mie3-mvcrl.c
> index 57b08e48d0..f749dad9c2 100644
> --- a/tests/tcg/s390x/mie3-mvcrl.c
> +++ b/tests/tcg/s390x/mie3-mvcrl.c
> @@ -1,15 +1,17 @@
>  #include <stdint.h>
>  #include <string.h>
>
> +
>  static inline void mvcrl_8(const char *dst, const char *src)
>  {
>      asm volatile (
> -    "llill %%r0, 8\n"
> -    ".insn sse, 0xE50A00000000, 0(%[dst]), 0(%[src])"
> -    : : [dst] "d" (dst), [src] "d" (src)
> -    : "memory");
> +        "llill %%r0, 8\n"
> +        ".insn sse, 0xE50A00000000, 0(%[dst]), 0(%[src])"
> +        : : [dst] "d" (dst), [src] "d" (src)
> +        : "r0", "memory");
>  }
>
> +
>  int main(int argc, char *argv[])
>  {
>      const char *alpha = "abcdefghijklmnop";
> @@ -25,3 +27,5 @@ int main(int argc, char *argv[])
>
>      return strncmp(alpha, tstr, 16ul);
>  }
> +
> +
> diff --git a/tests/tcg/s390x/mie3-sel.c b/tests/tcg/s390x/mie3-sel.c
> index b0c5c9857d..98cf4d40f5 100644
> --- a/tests/tcg/s390x/mie3-sel.c
> +++ b/tests/tcg/s390x/mie3-sel.c
> @@ -1,29 +1,32 @@
>  #include <stdint.h>
>
> +
>  #define Fi3(S, ASM) uint64_t S(uint64_t a, uint64_t b, uint64_t c) \
> -{                            \
> -    uint64_t res = 0;        \
> -    asm (                    \
> -         "lg %%r2, %[a]\n"   \
> -         "lg %%r3, %[b]\n"   \
> -         "lg %%r0, %[c]\n"   \
> -         "ltgr %%r0, %%r0\n" \
> -         ASM                 \
> -         "stg %%r0, %[res] " \
> -         : [res] "=m" (res)  \
> -         : [a] "m" (a),      \
> -           [b] "m" (b),      \
> -           [c] "m" (c)       \
> -         : "r0", "r2",       \
> -           "r3", "r4"        \
> -    );                       \
> -    return res;              \
> +{                       \
> +    uint64_t res = 0;   \
> +asm volatile (          \
> +    "lg %%r2, %[a]\n"   \
> +    "lg %%r3, %[b]\n"   \
> +    "lg %%r0, %[c]\n"   \
> +    "ltgr %%r0, %%r0\n" \
> +    ASM                 \
> +    "stg %%r0, %[res] " \
> +    : [res] "=m" (res)  \
> +    : [a] "m" (a),      \
> +      [b] "m" (b),      \
> +      [c] "m" (c)       \
> +    : "r0", "r2",       \
> +      "r3", "r4"        \
> +);                      \
> +    return res;         \
>  }
>
> +
>  Fi3 (_selre,     ".insn rrf, 0xB9F00000, %%r0, %%r3, %%r2, 8\n")
>  Fi3 (_selgrz,    ".insn rrf, 0xB9E30000, %%r0, %%r3, %%r2, 8\n")
>  Fi3 (_selfhrnz,  ".insn rrf, 0xB9C00000, %%r0, %%r3, %%r2, 7\n")
>
> +
>  int main(int argc, char *argv[])
>  {
>      uint64_t a = ~0, b = ~0, c = ~0;
> @@ -34,5 +37,6 @@ int main(int argc, char *argv[])
>      return (int) (
>          (0xFFFFFFFF00000066ull != a) ||
>          (0x0000F00D00000005ull != b) ||
> -        (0x00000654FFFFFFFFull != c));
> +        (0x00000654FFFFFFFFull != c) );
>  }
> +
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/tests/tcg/s390x/mie3-compl.c b/tests/tcg/s390x/mie3-compl.c
index 35649f3b02..85b23a9b7a 100644
--- a/tests/tcg/s390x/mie3-compl.c
+++ b/tests/tcg/s390x/mie3-compl.c
@@ -1,32 +1,44 @@ 
 #include <stdint.h>
 
+
 #define FbinOp(S, ASM) uint64_t S(uint64_t a, uint64_t b) \
-{ \
-    uint64_t res = 0; \
-    asm ("llihf %[res],801\n" ASM \
-         : [res]"=&r"(res) : [a]"r"(a), [b]"r"(b) : "cc"); \
-    return res; \
+{                       \
+    uint64_t res = 0;   \
+asm volatile (          \
+    "llihf %%r0,801\n"  \
+    "lg %%r2, %[a]\n"   \
+    "lg %%r3, %[b]\n"   \
+    ASM                 \
+    "stg %%r0, %[res] " \
+    : [res] "=m" (res)  \
+    : [a] "m" (a)       \
+    , [b] "m" (b)       \
+    : "r0", "r2", "r3"  \
+);                      \
+    return res;         \
 }
 
+
 /* AND WITH COMPLEMENT */
-FbinOp(_ncrk,  ".insn rrf, 0xB9F50000, %[res], %[b], %[a], 0\n")
-FbinOp(_ncgrk, ".insn rrf, 0xB9E50000, %[res], %[b], %[a], 0\n")
+FbinOp(_ncrk,  ".insn rrf, 0xB9F50000, %%r0, %%r3, %%r2, 0\n")
+FbinOp(_ncgrk, ".insn rrf, 0xB9E50000, %%r0, %%r3, %%r2, 0\n")
 
 /* NAND */
-FbinOp(_nnrk,  ".insn rrf, 0xB9740000, %[res], %[b], %[a], 0\n")
-FbinOp(_nngrk, ".insn rrf, 0xB9640000, %[res], %[b], %[a], 0\n")
+FbinOp(_nnrk,  ".insn rrf, 0xB9740000, %%r0, %%r3, %%r2, 0\n")
+FbinOp(_nngrk, ".insn rrf, 0xB9640000, %%r0, %%r3, %%r2, 0\n")
 
 /* NOT XOR */
-FbinOp(_nxrk,  ".insn rrf, 0xB9770000, %[res], %[b], %[a], 0\n")
-FbinOp(_nxgrk, ".insn rrf, 0xB9670000, %[res], %[b], %[a], 0\n")
+FbinOp(_nxrk,  ".insn rrf, 0xB9770000, %%r0, %%r3, %%r2, 0\n")
+FbinOp(_nxgrk, ".insn rrf, 0xB9670000, %%r0, %%r3, %%r2, 0\n")
 
 /* NOR */
-FbinOp(_nork,  ".insn rrf, 0xB9760000, %[res], %[b], %[a], 0\n")
-FbinOp(_nogrk, ".insn rrf, 0xB9660000, %[res], %[b], %[a], 0\n")
+FbinOp(_nork,  ".insn rrf, 0xB9760000, %%r0, %%r3, %%r2, 0\n")
+FbinOp(_nogrk, ".insn rrf, 0xB9660000, %%r0, %%r3, %%r2, 0\n")
 
 /* OR WITH COMPLEMENT */
-FbinOp(_ocrk,  ".insn rrf, 0xB9750000, %[res], %[b], %[a], 0\n")
-FbinOp(_ocgrk, ".insn rrf, 0xB9650000, %[res], %[b], %[a], 0\n")
+FbinOp(_ocrk,  ".insn rrf, 0xB9750000, %%r0, %%r3, %%r2, 0\n")
+FbinOp(_ocgrk, ".insn rrf, 0xB9650000, %%r0, %%r3, %%r2, 0\n")
+
 
 int main(int argc, char *argv[])
 {
diff --git a/tests/tcg/s390x/mie3-mvcrl.c b/tests/tcg/s390x/mie3-mvcrl.c
index 57b08e48d0..f749dad9c2 100644
--- a/tests/tcg/s390x/mie3-mvcrl.c
+++ b/tests/tcg/s390x/mie3-mvcrl.c
@@ -1,15 +1,17 @@ 
 #include <stdint.h>
 #include <string.h>
 
+
 static inline void mvcrl_8(const char *dst, const char *src)
 {
     asm volatile (
-    "llill %%r0, 8\n"
-    ".insn sse, 0xE50A00000000, 0(%[dst]), 0(%[src])"
-    : : [dst] "d" (dst), [src] "d" (src)
-    : "memory");
+        "llill %%r0, 8\n"
+        ".insn sse, 0xE50A00000000, 0(%[dst]), 0(%[src])"
+        : : [dst] "d" (dst), [src] "d" (src)
+        : "r0", "memory");
 }
 
+
 int main(int argc, char *argv[])
 {
     const char *alpha = "abcdefghijklmnop";
@@ -25,3 +27,5 @@  int main(int argc, char *argv[])
 
     return strncmp(alpha, tstr, 16ul);
 }
+
+
diff --git a/tests/tcg/s390x/mie3-sel.c b/tests/tcg/s390x/mie3-sel.c
index b0c5c9857d..98cf4d40f5 100644
--- a/tests/tcg/s390x/mie3-sel.c
+++ b/tests/tcg/s390x/mie3-sel.c
@@ -1,29 +1,32 @@ 
 #include <stdint.h>
 
+
 #define Fi3(S, ASM) uint64_t S(uint64_t a, uint64_t b, uint64_t c) \
-{                            \
-    uint64_t res = 0;        \
-    asm (                    \
-         "lg %%r2, %[a]\n"   \
-         "lg %%r3, %[b]\n"   \
-         "lg %%r0, %[c]\n"   \
-         "ltgr %%r0, %%r0\n" \
-         ASM                 \
-         "stg %%r0, %[res] " \
-         : [res] "=m" (res)  \
-         : [a] "m" (a),      \
-           [b] "m" (b),      \
-           [c] "m" (c)       \
-         : "r0", "r2",       \
-           "r3", "r4"        \
-    );                       \
-    return res;              \
+{                       \
+    uint64_t res = 0;   \
+asm volatile (          \
+    "lg %%r2, %[a]\n"   \
+    "lg %%r3, %[b]\n"   \
+    "lg %%r0, %[c]\n"   \
+    "ltgr %%r0, %%r0\n" \
+    ASM                 \
+    "stg %%r0, %[res] " \
+    : [res] "=m" (res)  \
+    : [a] "m" (a),      \
+      [b] "m" (b),      \
+      [c] "m" (c)       \
+    : "r0", "r2",       \
+      "r3", "r4"        \
+);                      \
+    return res;         \
 }
 
+
 Fi3 (_selre,     ".insn rrf, 0xB9F00000, %%r0, %%r3, %%r2, 8\n")
 Fi3 (_selgrz,    ".insn rrf, 0xB9E30000, %%r0, %%r3, %%r2, 8\n")
 Fi3 (_selfhrnz,  ".insn rrf, 0xB9C00000, %%r0, %%r3, %%r2, 7\n")
 
+
 int main(int argc, char *argv[])
 {
     uint64_t a = ~0, b = ~0, c = ~0;
@@ -34,5 +37,6 @@  int main(int argc, char *argv[])
     return (int) (
         (0xFFFFFFFF00000066ull != a) ||
         (0x0000F00D00000005ull != b) ||
-        (0x00000654FFFFFFFFull != c));
+        (0x00000654FFFFFFFFull != c) );
 }
+