diff mbox series

[PULL,31/33] target: Use ArchCPU as interface to target CPU

Message ID 20220306130000.8104-32-philippe.mathieu.daude@gmail.com (mailing list archive)
State New, archived
Headers show
Series [PULL,01/33] accel: Restrict sysemu stubs to system emulation | expand

Commit Message

Philippe Mathieu-Daudé March 6, 2022, 12:59 p.m. UTC 
From: Philippe Mathieu-Daudé <f4bug@amsat.org>

ArchCPU is our interface with target-specific code. Use it as
a forward-declared opaque pointer (abstract type), having its
structure defined by each target.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220214183144.27402-15-f4bug@amsat.org>
---
 include/hw/core/cpu.h   | 4 ++--
 include/qemu/typedefs.h | 1 +
 target/alpha/cpu.h      | 2 +-
 target/arm/cpu.h        | 2 +-
 target/avr/cpu.h        | 2 +-
 target/cris/cpu.h       | 2 +-
 target/hexagon/cpu.h    | 2 +-
 target/hppa/cpu.h       | 2 +-
 target/i386/cpu.h       | 2 +-
 target/m68k/cpu.h       | 2 +-
 target/microblaze/cpu.h | 2 +-
 target/mips/cpu.h       | 2 +-
 target/nios2/cpu.h      | 2 +-
 target/openrisc/cpu.h   | 2 +-
 target/ppc/cpu.h        | 2 +-
 target/riscv/cpu.h      | 2 +-
 target/rx/cpu.h         | 2 +-
 target/s390x/cpu.h      | 2 +-
 target/sh4/cpu.h        | 2 +-
 target/sparc/cpu.h      | 2 +-
 target/tricore/cpu.h    | 2 +-
 target/xtensa/cpu.h     | 2 +-
 22 files changed, 23 insertions(+), 22 deletions(-)
diff mbox series

Patch

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 2a0893b1dc7..0efc6153ed0 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -70,8 +70,8 @@  DECLARE_CLASS_CHECKERS(CPUClass, CPU,
  * The object struct and class struct need to be declared manually.
  */
 #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \
-    OBJECT_DECLARE_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME); \
-    typedef CpuInstanceType ArchCPU;
+    typedef struct ArchCPU CpuInstanceType; \
+    OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME);
 
 typedef enum MMUAccessType {
     MMU_DATA_LOAD  = 0,
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index c6f692b0dd5..c564f54c112 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -26,6 +26,7 @@  typedef struct AddressSpace AddressSpace;
 typedef struct AioContext AioContext;
 typedef struct Aml Aml;
 typedef struct AnnounceTimer AnnounceTimer;
+typedef struct ArchCPU ArchCPU;
 typedef struct BdrvDirtyBitmap BdrvDirtyBitmap;
 typedef struct BdrvDirtyBitmapIter BdrvDirtyBitmapIter;
 typedef struct BlockBackend BlockBackend;
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 84430aff421..58f00b7814f 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -257,7 +257,7 @@  typedef struct CPUArchState {
  *
  * An Alpha CPU.
  */
-struct AlphaCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index af89509f5a9..0b4b5bbf54c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -774,7 +774,7 @@  typedef struct ARMISARegisters ARMISARegisters;
  *
  * An ARM CPU core.
  */
-struct ARMCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index a833799fc14..55497f851dc 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -143,7 +143,7 @@  typedef struct CPUArchState {
  *
  *  A AVR CPU.
  */
-struct AVRCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index af7121bba06..e6776f25b17 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -173,7 +173,7 @@  typedef struct CPUArchState {
  *
  * A CRIS CPU.
  */
-struct CRISCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 8db0aa542d6..2a65a57bab3 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -140,7 +140,7 @@  typedef struct HexagonCPUClass {
     DeviceReset parent_reset;
 } HexagonCPUClass;
 
-struct HexagonCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 73a3f323895..4cc936b6bfd 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -213,7 +213,7 @@  typedef struct CPUArchState {
  *
  * An HPPA CPU.
  */
-struct HPPACPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index d99e175e17c..e11734ba866 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1707,7 +1707,7 @@  struct kvm_msrs;
  *
  * An x86 CPU.
  */
-struct X86CPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 76a7cc70b4f..872e8ce6375 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -156,7 +156,7 @@  typedef struct CPUArchState {
  *
  * A Motorola 68k CPU.
  */
-struct M68kCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 6e4e90a41ed..0a0ce71b6a5 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -339,7 +339,7 @@  typedef struct {
  *
  * A MicroBlaze CPU.
  */
-struct MicroBlazeCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
 
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index c361408cc81..09e98f64de5 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1171,7 +1171,7 @@  typedef struct CPUArchState {
  *
  * A MIPS CPU.
  */
-struct MIPSCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index e07da73df0d..ca0f3420cd1 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -169,7 +169,7 @@  struct CPUArchState {
  *
  * A Nios2 CPU.
  */
-struct Nios2CPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index bcd28802e49..bdf29d2dc4c 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -297,7 +297,7 @@  typedef struct CPUArchState {
  *
  * A OpenRISC CPU.
  */
-struct OpenRISCCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 03bba61c8b4..047b24ba50e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1275,7 +1275,7 @@  typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
  *
  * A PowerPC CPU.
  */
-struct PowerPCCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2810389fddb..c069fe85fa1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -394,7 +394,7 @@  typedef struct RISCVCPUConfig RISCVCPUConfig;
  *
  * A RISCV CPU.
  */
-struct RISCVCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index f81bf5b592a..b4abd90ccd1 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -105,7 +105,7 @@  typedef struct CPUArchState {
  *
  * A RX CPU
  */
-struct RXCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index bdf3f7d4feb..c49c8466e74 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -163,7 +163,7 @@  static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
  *
  * An S/390 CPU.
  */
-struct S390CPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index dd477ba5771..c72a30edfd4 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -195,7 +195,7 @@  typedef struct CPUArchState {
  *
  * A SuperH CPU.
  */
-struct SuperHCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 2a7fd47da3e..abb38db6749 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -556,7 +556,7 @@  struct CPUArchState {
  *
  * A SPARC CPU.
  */
-struct SPARCCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index cd1954aa9ed..108d6b8288f 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -196,7 +196,7 @@  typedef struct CPUArchState {
  *
  * A TriCore CPU.
  */
-struct TriCoreCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index a361ab87859..4515f682aa2 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -553,7 +553,7 @@  struct CPUArchState {
  *
  * An Xtensa CPU.
  */
-struct XtensaCPU {
+struct ArchCPU {
     /*< private >*/
     CPUState parent_obj;
     /*< public >*/