| Message ID | 20220307134353.1950-2-philippe.mathieu.daude@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw: ISA & MIPS patches from Bernhard Beschow | expand |
On 3/7/22 03:43, Philippe Mathieu-Daudé wrote: > From: Bernhard Beschow<shentey@gmail.com> > > Based on commit e735b55a8c11dd455e31ccd4420e6c9485191d0c: > > piix_pci: eliminate PIIX3State::pci_irq_levels > > PIIX3State::pci_irq_levels are redundant which is already tracked by > PCIBus layer. So eliminate them. > > The IRQ levels in the PCIBus layer are already preserved during > migration. By reusing them and rather than having a redundant implementation > the bug is avoided in the first place. > > Suggested-by: Peter Maydell<peter.maydell@linaro.org> > Signed-off-by: Bernhard Beschow<shentey@gmail.com> > Reviewed-by: Peter Maydell<peter.maydell@linaro.org> > Message-Id:<20220217101924.15347-2-shentey@gmail.com> > Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org> > --- > hw/mips/gt64xxx_pci.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index c7480bd019..4cbd0911f5 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1006,14 +1006,11 @@ static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num) } } -static int pci_irq_levels[4]; - static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) { int i, pic_irq, pic_level; qemu_irq *pic = opaque; - - pci_irq_levels[irq_num] = level; + PCIBus *bus = pci_get_bus(piix4_dev); /* now we change the pic irq level according to the piix irq mappings */ /* XXX: optimize */ @@ -1023,7 +1020,7 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) pic_level = 0; for (i = 0; i < 4; i++) { if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { - pic_level |= pci_irq_levels[i]; + pic_level |= pci_bus_get_irq_level(bus, i); } } qemu_set_irq(pic[pic_irq], pic_level);