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Thu, 10 Mar 2022 15:51:02 +0000 (GMT) Received: from localhost.ibm.com (unknown [9.101.4.17]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 83DB352051; Thu, 10 Mar 2022 15:51:02 +0000 (GMT) From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/3] ppc/pnv: Fix PEC lookup function for POWER10 Date: Thu, 10 Mar 2022 16:51:01 +0100 Message-Id: <20220310155101.294568-4-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220310155101.294568-1-fbarrat@linux.ibm.com> References: <20220310155101.294568-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: bIaJu2K69-OAV3JZ7ENI8-w1pGg8fxs3 X-Proofpoint-ORIG-GUID: yo6qOnecQFZWZei5U0lB1ujiShUqPkRZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-03-10_06,2022-03-09_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 suspectscore=0 mlxscore=0 spamscore=0 bulkscore=0 priorityscore=1501 mlxlogscore=856 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2203100084 Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The PEC array used when looking for the PEC hosting a PHB is stored in the chip structure. The array is at a different offset in Pnv9Chip and Pnv10Chip. The lookup function was therefore not working properly on POWER10. This patch fixes it by introducing a class method to get the correct PEC pointer based on the chip object and PEC index. Fixes: 623575e16cd5 ("ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge") Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater --- hw/pci-host/pnv_phb4.c | 5 ++--- hw/ppc/pnv.c | 14 ++++++++++++++ include/hw/ppc/pnv.h | 1 + 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index d1a911f988..4732633833 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1548,7 +1548,6 @@ static void pnv_phb4_instance_init(Object *obj) static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb, Error **errp) { - Pnv9Chip *chip9 = PNV9_CHIP(chip); int chip_id = phb->chip_id; int index = phb->phb_id; int i, j; @@ -1556,9 +1555,9 @@ static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb, for (i = 0; i < chip->num_pecs; i++) { /* * For each PEC, check the amount of phbs it supports - * and see if the given phb4 index matches an index. + * and see if the given phb index matches an index. */ - PnvPhb4PecState *pec = &chip9->pecs[i]; + PnvPhb4PecState *pec = PNV_CHIP_GET_CLASS(chip)->get_pec(chip, i); for (j = 0; j < pec->num_phbs; j++) { if (index == pnv_phb4_pec_get_phb_id(pec, j)) { diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index df58403a3a..3a676cd570 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1561,6 +1561,12 @@ static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) return addr >> 3; } +static PnvPhb4PecState *pnv_chip_power9_get_pec(PnvChip *chip, uint32_t index) +{ + Pnv9Chip *chip9 = PNV9_CHIP(chip); + return &chip9->pecs[index]; +} + static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1580,6 +1586,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) k->xscom_pcba = pnv_chip_power9_xscom_pcba; dc->desc = "PowerNV Chip POWER9"; k->num_pecs = PNV9_CHIP_MAX_PEC; + k->get_pec = pnv_chip_power9_get_pec; device_class_set_parent_realize(dc, pnv_chip_power9_realize, &k->parent_realize); @@ -1769,6 +1776,12 @@ static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) return addr >> 3; } +static PnvPhb4PecState *pnv_chip_power10_get_pec(PnvChip *chip, uint32_t index) +{ + Pnv10Chip *chip10 = PNV10_CHIP(chip); + return &chip10->pecs[index]; +} + static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -1788,6 +1801,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) k->xscom_pcba = pnv_chip_power10_xscom_pcba; dc->desc = "PowerNV Chip POWER10"; k->num_pecs = PNV10_CHIP_MAX_PEC; + k->get_pec = pnv_chip_power10_get_pec; device_class_set_parent_realize(dc, pnv_chip_power10_realize, &k->parent_realize); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 1e34ddd502..282f76ba08 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -163,6 +163,7 @@ struct PnvChipClass { void (*pic_print_info)(PnvChip *chip, Monitor *mon); uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); + PnvPhb4PecState *(*get_pec)(PnvChip *chip, uint32_t index); }; #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP