| Message ID | 20220321153357.165775-3-fbarrat@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Remove PCIE root bridge LSI on powernv | expand |
On 3/21/22 12:33, Frederic Barrat wrote: > The phb3/phb4/phb5 root ports inherit from the default PCIE root port > implementation, which requests a LSI interrupt (#INTA). On real > hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch > corrects it so that it matches the hardware. > > As a consequence, the device tree previously generated was bogus, as > the root bridge LSI was not properly mapped. On some > implementation (powernv9), it was leading to inconsistent interrupt > controller (xive) data. With this patch, it is now clean. > > Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> > --- Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> > hw/pci-host/pnv_phb3.c | 1 + > hw/pci-host/pnv_phb4.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c > index ac801ac835..0d18c96117 100644 > --- a/hw/pci-host/pnv_phb3.c > +++ b/hw/pci-host/pnv_phb3.c > @@ -1162,6 +1162,7 @@ static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp) > error_propagate(errp, local_err); > return; > } > + pci_config_set_interrupt_pin(pci->config, 0); > } > > static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data) > diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c > index b301762093..b66b75d4d7 100644 > --- a/hw/pci-host/pnv_phb4.c > +++ b/hw/pci-host/pnv_phb4.c > @@ -1772,6 +1772,7 @@ static void pnv_phb4_root_port_reset(DeviceState *dev) > pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); > pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ > pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); > + pci_config_set_interrupt_pin(conf, 0); > } > > static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index ac801ac835..0d18c96117 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -1162,6 +1162,7 @@ static void pnv_phb3_root_port_realize(DeviceState *dev, Error **errp) error_propagate(errp, local_err); return; } + pci_config_set_interrupt_pin(pci->config, 0); } static void pnv_phb3_root_port_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index b301762093..b66b75d4d7 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1772,6 +1772,7 @@ static void pnv_phb4_root_port_reset(DeviceState *dev) pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); + pci_config_set_interrupt_pin(conf, 0); } static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp)
The phb3/phb4/phb5 root ports inherit from the default PCIE root port implementation, which requests a LSI interrupt (#INTA). On real hardware (POWER8/POWER9/POWER10), there is no such LSI. This patch corrects it so that it matches the hardware. As a consequence, the device tree previously generated was bogus, as the root bridge LSI was not properly mapped. On some implementation (powernv9), it was leading to inconsistent interrupt controller (xive) data. With this patch, it is now clean. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> --- hw/pci-host/pnv_phb3.c | 1 + hw/pci-host/pnv_phb4.c | 1 + 2 files changed, 2 insertions(+)