diff mbox series

[v1,01/43] target/loongarch: Add README

Message ID	20220415094058.3584233-2-yangxiaojuan@loongson.cn (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: Xiaojuan Yang <yangxiaojuan@loongson.cn> To: qemu-devel@nongnu.org Subject: [PATCH v1 01/43] target/loongarch: Add README Date: Fri, 15 Apr 2022 17:40:16 +0800 Message-Id: <20220415094058.3584233-2-yangxiaojuan@loongson.cn> In-Reply-To: <20220415094058.3584233-1-yangxiaojuan@loongson.cn> References: <20220415094058.3584233-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: mark.cave-ayland@ilande.co.uk, richard.henderson@linaro.org, gaosong@loongson.cn Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	Add LoongArch softmmu support \| expand [v1,00/43] Add LoongArch softmmu support [v1,01/43] target/loongarch: Add README [v1,02/43] target/loongarch: Add core definition [v1,03/43] target/loongarch: Add main translation routines [v1,04/43] target/loongarch: Add fixed point arithmetic instruction translation [v1,05/43] target/loongarch: Add fixed point shift instruction translation [v1,06/43] target/loongarch: Add fixed point bit instruction translation [v1,07/43] target/loongarch: Add fixed point load/store instruction translation [v1,08/43] target/loongarch: Add fixed point atomic instruction translation [v1,09/43] target/loongarch: Add fixed point extra instruction translation [v1,10/43] target/loongarch: Add floating point arithmetic instruction translation [v1,11/43] target/loongarch: Add floating point comparison instruction translation [v1,12/43] target/loongarch: Add floating point conversion instruction translation [v1,13/43] target/loongarch: Add floating point move instruction translation [v1,14/43] target/loongarch: Add floating point load/store instruction translation [v1,15/43] target/loongarch: Add branch instruction translation [v1,16/43] target/loongarch: Add disassembler [v1,17/43] target/loongarch: Add target build suport [v1,18/43] target/loongarch: Add system emulation introduction [v1,19/43] target/loongarch: Add CSRs definition [v1,20/43] target/loongarch: Add basic vmstate description of CPU. [v1,21/43] target/loongarch: Implement qmp_query_cpu_definitions() [v1,22/43] target/loongarch: Add MMU support for LoongArch CPU. [v1,23/43] target/loongarch: Add LoongArch interrupt and exception handle [v1,24/43] target/loongarch: Add constant timer support [v1,25/43] target/loongarch: Add LoongArch CSR instruction [v1,26/43] target/loongarch: Add LoongArch IOCSR instruction [v1,27/43] target/loongarch: Add TLB instruction support [v1,28/43] target/loongarch: Add other core instructions support [v1,29/43] target/loongarch: Add timer related instructions support. [v1,30/43] target/loongarch: Add gdb support. [v1,31/43] hw/loongarch: Add support loongson3 virt machine type. [v1,32/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) [v1,33/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) [v1,34/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) [v1,35/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) [v1,36/43] hw/loongarch: Add irq hierarchy for the system [v1,37/43] Enable common virtio pci support for LoongArch [v1,38/43] hw/loongarch: Add some devices support for 3A5000. [v1,39/43] hw/loongarch: Add LoongArch ls7a rtc device support [v1,40/43] hw/loongarch: Add LoongArch boot code and load elf function. [v1,41/43] hw/loongarch: Add LoongArch ls7a acpi device support [v1,42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system [v1,43/43] target/loongarch: 'make check-tcg' support

Commit Message

Xiaojuan Yang April 15, 2022, 9:40 a.m. UTC

From: Song Gao <gaosong@loongson.cn>

This patch gives an introduction to the LoongArch target.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 MAINTAINERS             |  6 ++++++
 target/loongarch/README | 10 ++++++++++
 2 files changed, 16 insertions(+)
 create mode 100644 target/loongarch/README

diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 4ad2451e03..94255cb04e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -213,6 +213,12 @@  S: Maintained
 F: target/hppa/
 F: disas/hppa.c
 
+LoongArch TCG CPUs
+M: Song Gao <gaosong@loongson.cn>
+M: Xiaojuan Yang <yangxiaojuan@loongson.cn>
+S: Maintained
+F: target/loongarch/
+
 M68K TCG CPUs
 M: Laurent Vivier <laurent@vivier.eu>
 S: Maintained
diff --git a/target/loongarch/README b/target/loongarch/README
new file mode 100644
index 0000000000..de141c1a58
--- /dev/null
+++ b/target/loongarch/README
@@ -0,0 +1,10 @@ 
+- Introduction
+
+  LoongArch is the general processor architecture of Loongson.
+
+  The following versions of the LoongArch core are supported
+    core: 3A5000
+    https://github.com/loongson/LoongArch-Documentation/releases/download/2021.08.17/LoongArch-Vol1-v1.00-EN.pdf
+
+  We can get the latest loongarch documents at https://github.com/loongson/LoongArch-Documentation/tags.
+