From patchwork Fri Apr 15 09:40:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaojuan Yang X-Patchwork-Id: 12814767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4C19CC433EF for ; Fri, 15 Apr 2022 10:32:08 +0000 (UTC) Received: from localhost ([::1]:33796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nfJFH-00072O-Cc for qemu-devel@archiver.kernel.org; Fri, 15 Apr 2022 06:32:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35668) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nfIXs-0000B0-9o for qemu-devel@nongnu.org; Fri, 15 Apr 2022 05:47:16 -0400 Received: from mail.loongson.cn ([114.242.206.163]:55734 helo=loongson.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nfIXo-0005Ol-3g for qemu-devel@nongnu.org; Fri, 15 Apr 2022 05:47:16 -0400 Received: from localhost.localdomain (unknown [10.2.5.185]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dx_xGqPVli41gkAA--.16856S31; Fri, 15 Apr 2022 17:41:31 +0800 (CST) From: Xiaojuan Yang To: qemu-devel@nongnu.org Subject: [PATCH v1 29/43] target/loongarch: Add timer related instructions support. Date: Fri, 15 Apr 2022 17:40:44 +0800 Message-Id: <20220415094058.3584233-30-yangxiaojuan@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220415094058.3584233-1-yangxiaojuan@loongson.cn> References: <20220415094058.3584233-1-yangxiaojuan@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Dx_xGqPVli41gkAA--.16856S31 X-Coremail-Antispam: 1UD129KBjvJXoWxGry8AryDXFW8tF13AFy7Jrb_yoWrZF1rpr 4I9ryUKrW8JrZxZ3Z3tas8Xr15Xw4xCF42qa93t3s5CF47X3ZrZr18t3sxKF45Xa1DXryj qa1kA34j9FWxXaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: p1dqw5xldry3tdq6z05rqj20fqof0/ Received-SPF: pass client-ip=114.242.206.163; envelope-from=yangxiaojuan@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.cave-ayland@ilande.co.uk, richard.henderson@linaro.org, gaosong@loongson.cn Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This includes: -RDTIME{L/H}.W -RDTIME.D Signed-off-by: Xiaojuan Yang Signed-off-by: Song Gao --- target/loongarch/disas.c | 3 ++ target/loongarch/helper.h | 2 ++ target/loongarch/insn_trans/trans_extra.c.inc | 33 +++++++++++++++++++ target/loongarch/insns.decode | 3 ++ target/loongarch/op_helper.c | 11 +++++++ target/loongarch/translate.c | 2 ++ 6 files changed, 54 insertions(+) diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 4ce00012a8..a2a27eee33 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -266,6 +266,9 @@ INSN(bitrev_w, rr) INSN(bitrev_d, rr) INSN(ext_w_h, rr) INSN(ext_w_b, rr) +INSN(rdtimel_w, rr) +INSN(rdtimeh_w, rr) +INSN(rdtime_d, rr) INSN(cpucfg, rr) INSN(asrtle_d, rr_jk) INSN(asrtgt_d, rr_jk) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index ad1a43d162..ce50e99dfc 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -93,6 +93,8 @@ DEF_HELPER_2(frint_d, i64, env, i64) DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_1(rdtime_d, i64, env) + /* CSRs helper */ DEF_HELPER_1(csrrd_pgd, i64, env) DEF_HELPER_1(csrrd_tval, i64, env) diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc index 549f75a867..ad713cd61e 100644 --- a/target/loongarch/insn_trans/trans_extra.c.inc +++ b/target/loongarch/insn_trans/trans_extra.c.inc @@ -33,6 +33,39 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a) return true; } +static bool gen_rdtime(DisasContext *ctx, arg_rr *a, + bool word, bool high) +{ + TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE); + TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE); + + if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_rdtime_d(dst1, cpu_env); + if (word) { + tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32); + } + tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TID)); + + return true; +} + +static bool trans_rdtimel_w(DisasContext *ctx, arg_rdtimel_w *a) +{ + return gen_rdtime(ctx, a, 1, 0); +} + +static bool trans_rdtimeh_w(DisasContext *ctx, arg_rdtimeh_w *a) +{ + return gen_rdtime(ctx, a, 1, 1); +} + +static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a) +{ + return gen_rdtime(ctx, a, 0, 0); +} + static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index ebd3d505fb..3fdc6e148c 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -309,6 +309,9 @@ break 0000 00000010 10100 ............... @i15 syscall 0000 00000010 10110 ............... @i15 asrtle_d 0000 00000000 00010 ..... ..... 00000 @rr_jk asrtgt_d 0000 00000000 00011 ..... ..... 00000 @rr_jk +rdtimel_w 0000 00000000 00000 11000 ..... ..... @rr +rdtimeh_w 0000 00000000 00000 11001 ..... ..... @rr +rdtime_d 0000 00000000 00000 11010 ..... ..... @rr cpucfg 0000 00000000 00000 11011 ..... ..... @rr # diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c index 2243fcfa44..57482c743a 100644 --- a/target/loongarch/op_helper.c +++ b/target/loongarch/op_helper.c @@ -84,6 +84,17 @@ target_ulong helper_cpucfg(CPULoongArchState *env, target_ulong rj) return rj > 21 ? 0 : env->cpucfg[rj]; } +uint64_t helper_rdtime_d(CPULoongArchState *env) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(env_cpu(env)); + + if ((env->CSR_MISC >> 7) & 0x1) { + do_raise_exception(env, EXCCODE_IPE, GETPC()); + } + + return cpu_loongarch_get_constant_timer_counter(cpu); +} + void helper_ertn(CPULoongArchState *env) { uint64_t csr_pplv, csr_pie; diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index c1cac2f006..9ce003980d 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -25,6 +25,8 @@ static TCGv cpu_lladdr, cpu_llval; TCGv_i32 cpu_fcsr0; TCGv_i64 cpu_fpr[32]; +#include "exec/gen-icount.h" + #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1