@@ -91,6 +91,9 @@
@X_tp_a_bp_rc ...... ....0 ra:5 ....0 .......... rc:1 &X_rc rt=%x_frtp rb=%x_frbp
+&X_t_rc rt rc:bool
+@X_t_rc ...... rt:5 ..... ..... .......... rc:1 &X_t_rc
+
&X_tb_rc rt rb rc:bool
@X_tb_rc ...... rt:5 ..... rb:5 .......... rc:1 &X_tb_rc
@@ -312,6 +315,10 @@ SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi
SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi
SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi
+### Move To/From FPSCR
+
+MFFS 111111 ..... 00000 ----- 1001000111 . @X_t_rc
+
### Decimal Floating-Point Arithmetic Instructions
DADD 111011 ..... ..... ..... 0000000010 . @X_rc
@@ -607,6 +607,31 @@ static void gen_mffs(DisasContext *ctx)
tcg_temp_free_i64(t0);
}
+static void do_mffsc(int rt)
+{
+ TCGv_i64 fpscr;
+
+ fpscr = tcg_temp_new_i64();
+
+ gen_reset_fpstatus();
+ tcg_gen_extu_tl_i64(fpscr, cpu_fpscr);
+ set_fpr(rt, fpscr);
+
+ tcg_temp_free_i64(fpscr);
+}
+
+static bool trans_MFFS(DisasContext *ctx, arg_X_t_rc *a)
+{
+ REQUIRE_FPU(ctx);
+
+ do_mffsc(a->rt);
+ if (a->rc) {
+ gen_set_cr1_from_fpscr(ctx);
+ }
+
+ return true;
+}
+
/* mffsl */
static void gen_mffsl(DisasContext *ctx)
{
@@ -75,7 +75,6 @@ GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
-GEN_HANDLER_E_2(mffs, 0x3F, 0x07, 0x12, 0x00, 0x00000000, PPC_FLOAT, PPC_NONE),
GEN_HANDLER_E_2(mffsce, 0x3F, 0x07, 0x12, 0x01, 0x00000000, PPC_FLOAT,
PPC2_ISA300),
GEN_HANDLER_E_2(mffsl, 0x3F, 0x07, 0x12, 0x18, 0x00000000, PPC_FLOAT,
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> --- target/ppc/insn32.decode | 7 +++++++ target/ppc/translate/fp-impl.c.inc | 25 +++++++++++++++++++++++++ target/ppc/translate/fp-ops.c.inc | 1 - 3 files changed, 32 insertions(+), 1 deletion(-)